dram_rot_gen.hh (12804:f47e75dce5c6) dram_rot_gen.hh (12811:269967d5b4e4)
1/*
1/*
2 * Copyright (c) 2012-2013, 2017 ARM Limited
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed here under. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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61
62 /**
63 * Create a DRAM address sequence generator.
64 * This sequence generator will rotate through:
65 * 1) Banks per rank
66 * 2) Command type (if applicable)
67 * 3) Ranks per channel
68 *
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed here under. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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61
62 /**
63 * Create a DRAM address sequence generator.
64 * This sequence generator will rotate through:
65 * 1) Banks per rank
66 * 2) Command type (if applicable)
67 * 3) Ranks per channel
68 *
69 * @param _name Name to use for status and debug
70 * @param master_id MasterID set on each request
69 * @param gen Traffic generator owning this sequence generator
71 * @param _duration duration of this state before transitioning
72 * @param start_addr Start address
73 * @param end_addr End address
74 * @param _blocksize Size used for transactions injected
75 * @param min_period Lower limit of random inter-transaction time
76 * @param max_period Upper limit of random inter-transaction time
77 * @param read_percent Percent of transactions that are reads
78 * @param data_limit Upper limit on how much data to read/write
79 * @param num_seq_pkts Number of packets per stride, each of _blocksize
80 * @param page_size Page size (bytes) used in the DRAM
81 * @param nbr_of_banks_DRAM Total number of banks in DRAM
82 * @param nbr_of_banks_util Number of banks to utilized,
83 * for N banks, we will use banks: 0->(N-1)
84 * @param nbr_of_ranks Number of ranks utilized,
85 * @param addr_mapping Address mapping to be used,
86 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
87 * assumes single channel system
88 */
70 * @param _duration duration of this state before transitioning
71 * @param start_addr Start address
72 * @param end_addr End address
73 * @param _blocksize Size used for transactions injected
74 * @param min_period Lower limit of random inter-transaction time
75 * @param max_period Upper limit of random inter-transaction time
76 * @param read_percent Percent of transactions that are reads
77 * @param data_limit Upper limit on how much data to read/write
78 * @param num_seq_pkts Number of packets per stride, each of _blocksize
79 * @param page_size Page size (bytes) used in the DRAM
80 * @param nbr_of_banks_DRAM Total number of banks in DRAM
81 * @param nbr_of_banks_util Number of banks to utilized,
82 * for N banks, we will use banks: 0->(N-1)
83 * @param nbr_of_ranks Number of ranks utilized,
84 * @param addr_mapping Address mapping to be used,
85 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
86 * assumes single channel system
87 */
89 DramRotGen(const std::string& _name, MasterID master_id, Tick _duration,
88 DramRotGen(BaseTrafficGen &gen, Tick _duration,
90 Addr start_addr, Addr end_addr, Addr _blocksize,
91 Tick min_period, Tick max_period,
92 uint8_t read_percent, Addr data_limit,
93 unsigned int num_seq_pkts, unsigned int page_size,
94 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
95 unsigned int addr_mapping,
96 unsigned int nbr_of_ranks,
97 unsigned int max_seq_count_per_rank)
89 Addr start_addr, Addr end_addr, Addr _blocksize,
90 Tick min_period, Tick max_period,
91 uint8_t read_percent, Addr data_limit,
92 unsigned int num_seq_pkts, unsigned int page_size,
93 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
94 unsigned int addr_mapping,
95 unsigned int nbr_of_ranks,
96 unsigned int max_seq_count_per_rank)
98 : DramGen(_name, master_id, _duration, start_addr, end_addr,
97 : DramGen(gen, _duration, start_addr, end_addr,
99 _blocksize, min_period, max_period, read_percent, data_limit,
100 num_seq_pkts, page_size, nbr_of_banks_DRAM,
101 nbr_of_banks_util, addr_mapping,
102 nbr_of_ranks),
103 maxSeqCountPerRank(max_seq_count_per_rank),
104 nextSeqCount(0)
105 {
106 // Rotating traffic generation can only support a read

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99 num_seq_pkts, page_size, nbr_of_banks_DRAM,
100 nbr_of_banks_util, addr_mapping,
101 nbr_of_ranks),
102 maxSeqCountPerRank(max_seq_count_per_rank),
103 nextSeqCount(0)
104 {
105 // Rotating traffic generation can only support a read

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