1/*
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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61
62 /**
63 * Create a DRAM address sequence generator.
64 * This sequence generator will rotate through:
65 * 1) Banks per rank
66 * 2) Command type (if applicable)
67 * 3) Ranks per channel
68 *
69 * @param obj SimObject owning this sequence generator
70 * @param master_id MasterID related to the memory requests
71 * @param _duration duration of this state before transitioning
72 * @param start_addr Start address
73 * @param end_addr End address
74 * @param _blocksize Size used for transactions injected
75 * @param cacheline_size cache line size in the system
76 * @param min_period Lower limit of random inter-transaction time
77 * @param max_period Upper limit of random inter-transaction time
78 * @param read_percent Percent of transactions that are reads
79 * @param data_limit Upper limit on how much data to read/write
80 * @param num_seq_pkts Number of packets per stride, each of _blocksize
81 * @param page_size Page size (bytes) used in the DRAM
82 * @param nbr_of_banks_DRAM Total number of banks in DRAM
83 * @param nbr_of_banks_util Number of banks to utilized,
84 * for N banks, we will use banks: 0->(N-1)
85 * @param nbr_of_ranks Number of ranks utilized,
86 * @param addr_mapping Address mapping to be used,
87 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
88 * assumes single channel system
89 */
90 DramRotGen(SimObject &obj, MasterID master_id, Tick _duration,
91 Addr start_addr, Addr end_addr,
92 Addr _blocksize, Addr cacheline_size,
93 Tick min_period, Tick max_period,
94 uint8_t read_percent, Addr data_limit,
95 unsigned int num_seq_pkts, unsigned int page_size,
96 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
97 unsigned int addr_mapping,
98 unsigned int nbr_of_ranks,
99 unsigned int max_seq_count_per_rank)
100 : DramGen(obj, master_id, _duration, start_addr, end_addr,
101 _blocksize, cacheline_size, min_period, max_period,
102 read_percent, data_limit,
103 num_seq_pkts, page_size, nbr_of_banks_DRAM,
104 nbr_of_banks_util, addr_mapping,
105 nbr_of_ranks),
106 maxSeqCountPerRank(max_seq_count_per_rank),
107 nextSeqCount(0)
108 {
109 // Rotating traffic generation can only support a read
110 // percentage of 0, 50, or 100

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