dram_rot_gen.cc (12396:3d04ea44fafb) dram_rot_gen.cc (12804:f47e75dce5c6)
1/*
2 * Copyright (c) 2012-2013, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed here under. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 * Sascha Bischoff
40 * Neha Agarwal
41 */
42
43#include "cpu/testers/traffic_gen/dram_rot_gen.hh"
44
45#include <algorithm>
46
47#include "base/random.hh"
48#include "base/trace.hh"
49#include "debug/TrafficGen.hh"
1/*
2 * Copyright (c) 2012-2013, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed here under. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 * Sascha Bischoff
40 * Neha Agarwal
41 */
42
43#include "cpu/testers/traffic_gen/dram_rot_gen.hh"
44
45#include <algorithm>
46
47#include "base/random.hh"
48#include "base/trace.hh"
49#include "debug/TrafficGen.hh"
50#include "proto/packet.pb.h"
51
52PacketPtr
53DramRotGen::getNextPacket()
54{
55 // if this is the first of the packets in series to be generated,
56 // start counting again
57 if (countNumSeqPkts == 0) {
58 countNumSeqPkts = numSeqPkts;
59
60 // choose if we generate a read or a write here
61 if (readPercent == 50) {
62 if ((nextSeqCount % nbrOfBanksUtil) == 0) {
63 // Change type after all banks have been rotated
64 // Otherwise, keep current value
65 isRead = !isRead;
66 }
67 } else {
68 // Set randomly based on percentage
69 isRead = readPercent != 0;
70 }
71
72 assert((readPercent == 0 && !isRead) ||
73 (readPercent == 100 && isRead) ||
74 readPercent != 100);
75
76 // Overwrite random bank value
77 // Rotate across banks
78 unsigned int new_bank = nextSeqCount % nbrOfBanksUtil;
79
80 // Overwrite random rank value
81 // Will rotate to the next rank after rotating through all banks,
82 // for each specified command type.
83
84 // Use modular function to ensure that calculated rank is within
85 // system limits after state transition
86 unsigned int new_rank = (nextSeqCount / maxSeqCountPerRank) %
87 nbrOfRanks;
88
89 // Increment nextSeqCount
90 // Roll back to 0 after completing a full rotation across
91 // banks, command type, and ranks
92 nextSeqCount = (nextSeqCount + 1) %
93 (nbrOfRanks * maxSeqCountPerRank);
94
95 DPRINTF(TrafficGen, "DramRotGen::getNextPacket nextSeqCount: %d "
96 "new_rank: %d new_bank: %d\n",
97 nextSeqCount, new_rank, new_bank);
98
99 // Generate the start address of the command series
100 // routine will update addr variable with bank, rank, and col
101 // bits updated for rotation scheme
102 genStartAddr(new_bank, new_rank);
103
104 } else {
105 // increment the column by one
106 if (addrMapping == 1)
107 // addrMapping=1: RoRaBaCoCh/RoRaBaChCo
108 // Simply increment addr by blocksize to
109 // increment the column by one
110 addr += blocksize;
111
112 else if (addrMapping == 0) {
113 // addrMapping=0: RoCoRaBaCh
114 // Explicity increment the column bits
115
116 unsigned int new_col = ((addr / blocksize /
117 nbrOfBanksDRAM / nbrOfRanks) %
118 (pageSize / blocksize)) + 1;
119 replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
120 blockBits + bankBits + rankBits, new_col);
121 }
122 }
123
124 DPRINTF(TrafficGen, "DramRotGen::getNextPacket: %c to addr %x, "
125 "size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
126 isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts);
127
128 // create a new request packet
129 PacketPtr pkt = getPacket(addr, blocksize,
130 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
131
132 // add the amount of data manipulated to the total
133 dataManipulated += blocksize;
134
135 // subtract the number of packets remained to be generated
136 --countNumSeqPkts;
137
138 // return the generated packet
139 return pkt;
140}
50
51PacketPtr
52DramRotGen::getNextPacket()
53{
54 // if this is the first of the packets in series to be generated,
55 // start counting again
56 if (countNumSeqPkts == 0) {
57 countNumSeqPkts = numSeqPkts;
58
59 // choose if we generate a read or a write here
60 if (readPercent == 50) {
61 if ((nextSeqCount % nbrOfBanksUtil) == 0) {
62 // Change type after all banks have been rotated
63 // Otherwise, keep current value
64 isRead = !isRead;
65 }
66 } else {
67 // Set randomly based on percentage
68 isRead = readPercent != 0;
69 }
70
71 assert((readPercent == 0 && !isRead) ||
72 (readPercent == 100 && isRead) ||
73 readPercent != 100);
74
75 // Overwrite random bank value
76 // Rotate across banks
77 unsigned int new_bank = nextSeqCount % nbrOfBanksUtil;
78
79 // Overwrite random rank value
80 // Will rotate to the next rank after rotating through all banks,
81 // for each specified command type.
82
83 // Use modular function to ensure that calculated rank is within
84 // system limits after state transition
85 unsigned int new_rank = (nextSeqCount / maxSeqCountPerRank) %
86 nbrOfRanks;
87
88 // Increment nextSeqCount
89 // Roll back to 0 after completing a full rotation across
90 // banks, command type, and ranks
91 nextSeqCount = (nextSeqCount + 1) %
92 (nbrOfRanks * maxSeqCountPerRank);
93
94 DPRINTF(TrafficGen, "DramRotGen::getNextPacket nextSeqCount: %d "
95 "new_rank: %d new_bank: %d\n",
96 nextSeqCount, new_rank, new_bank);
97
98 // Generate the start address of the command series
99 // routine will update addr variable with bank, rank, and col
100 // bits updated for rotation scheme
101 genStartAddr(new_bank, new_rank);
102
103 } else {
104 // increment the column by one
105 if (addrMapping == 1)
106 // addrMapping=1: RoRaBaCoCh/RoRaBaChCo
107 // Simply increment addr by blocksize to
108 // increment the column by one
109 addr += blocksize;
110
111 else if (addrMapping == 0) {
112 // addrMapping=0: RoCoRaBaCh
113 // Explicity increment the column bits
114
115 unsigned int new_col = ((addr / blocksize /
116 nbrOfBanksDRAM / nbrOfRanks) %
117 (pageSize / blocksize)) + 1;
118 replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
119 blockBits + bankBits + rankBits, new_col);
120 }
121 }
122
123 DPRINTF(TrafficGen, "DramRotGen::getNextPacket: %c to addr %x, "
124 "size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
125 isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts);
126
127 // create a new request packet
128 PacketPtr pkt = getPacket(addr, blocksize,
129 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
130
131 // add the amount of data manipulated to the total
132 dataManipulated += blocksize;
133
134 // subtract the number of packets remained to be generated
135 --countNumSeqPkts;
136
137 // return the generated packet
138 return pkt;
139}