1/*
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2 * Copyright (c) 2012-2013, 2017 ARM Limited
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2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed here under. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 * Neha Agarwal 41 */ 42 43/** 44 * @file 45 * Declaration of the DRAM generator for issuing variable page 46 * hit length requests and bank utilisation. 47 */ 48 49#ifndef __CPU_TRAFFIC_GEN_DRAM_GEN_HH__ 50#define __CPU_TRAFFIC_GEN_DRAM_GEN_HH__ 51 52#include "base/bitfield.hh" 53#include "base/intmath.hh" 54#include "mem/packet.hh" 55#include "random_gen.hh" 56 57/** 58 * DRAM specific generator is for issuing request with variable page 59 * hit length and bank utilization. Currently assumes a single 60 * channel configuration. 61 */ 62class DramGen : public RandomGen 63{ 64 65 public: 66 67 /** 68 * Create a DRAM address sequence generator. 69 *
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70 * @param _name Name to use for status and debug
71 * @param master_id MasterID set on each request
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70 * @param gen Traffic generator owning this sequence generator |
71 * @param _duration duration of this state before transitioning 72 * @param start_addr Start address 73 * @param end_addr End address 74 * @param _blocksize Size used for transactions injected 75 * @param min_period Lower limit of random inter-transaction time 76 * @param max_period Upper limit of random inter-transaction time 77 * @param read_percent Percent of transactions that are reads 78 * @param data_limit Upper limit on how much data to read/write 79 * @param num_seq_pkts Number of packets per stride, each of _blocksize 80 * @param page_size Page size (bytes) used in the DRAM 81 * @param nbr_of_banks_DRAM Total number of banks in DRAM 82 * @param nbr_of_banks_util Number of banks to utilized, 83 * for N banks, we will use banks: 0->(N-1) 84 * @param addr_mapping Address mapping to be used, 85 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo 86 * assumes single channel system 87 */
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89 DramGen(const std::string& _name, MasterID master_id, Tick _duration,
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88 DramGen(BaseTrafficGen &gen, Tick _duration, |
89 Addr start_addr, Addr end_addr, Addr _blocksize, 90 Tick min_period, Tick max_period, 91 uint8_t read_percent, Addr data_limit, 92 unsigned int num_seq_pkts, unsigned int page_size, 93 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, 94 unsigned int addr_mapping,
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96 unsigned int nbr_of_ranks)
97 : RandomGen(_name, master_id, _duration, start_addr, end_addr,
98 _blocksize, min_period, max_period, read_percent, data_limit),
99 numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
100 isRead(true), pageSize(page_size),
101 pageBits(floorLog2(page_size / _blocksize)),
102 bankBits(floorLog2(nbr_of_banks_DRAM)),
103 blockBits(floorLog2(_blocksize)),
104 nbrOfBanksDRAM(nbr_of_banks_DRAM),
105 nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping),
106 rankBits(floorLog2(nbr_of_ranks)),
107 nbrOfRanks(nbr_of_ranks)
108 {
109 if (addrMapping != 1 && addrMapping != 0) {
110 addrMapping = 1;
111 warn("Unknown address mapping specified, using RoRaBaCoCh\n");
112 }
113 }
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95 unsigned int nbr_of_ranks); |
96 97 PacketPtr getNextPacket(); 98 99 /** Insert bank, rank, and column bits into packed 100 * address to create address for 1st command in a 101 * series 102 * @param new_bank Bank number of next packet series 103 * @param new_rank Rank value of next packet series 104 */ 105 void genStartAddr(unsigned int new_bank , unsigned int new_rank); 106 107 protected: 108 109 /** Number of sequential DRAM packets to be generated per cpu request */ 110 const unsigned int numSeqPkts; 111 112 /** Track number of sequential packets generated for a request */ 113 unsigned int countNumSeqPkts; 114 115 /** Address of request */ 116 Addr addr; 117 118 /** Remember type of requests to be generated in series */ 119 bool isRead; 120 121 /** Page size of DRAM */ 122 const unsigned int pageSize; 123 124 /** Number of page bits in DRAM address */ 125 const unsigned int pageBits; 126 127 /** Number of bank bits in DRAM address*/ 128 const unsigned int bankBits; 129 130 /** Number of block bits in DRAM address */ 131 const unsigned int blockBits; 132 133 /** Number of banks in DRAM */ 134 const unsigned int nbrOfBanksDRAM; 135 136 /** Number of banks to be utilized for a given configuration */ 137 const unsigned int nbrOfBanksUtil; 138 139 /** Address mapping to be used */ 140 unsigned int addrMapping; 141 142 /** Number of rank bits in DRAM address*/ 143 const unsigned int rankBits; 144 145 /** Number of ranks to be utilized for a given configuration */ 146 const unsigned int nbrOfRanks; 147 148}; 149 150#endif
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