dram_gen.hh (12804:f47e75dce5c6) | dram_gen.hh (12811:269967d5b4e4) |
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1/* | 1/* |
2 * Copyright (c) 2012-2013, 2017 ARM Limited | 2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed here under. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 51 unchanged lines hidden (view full) --- 62class DramGen : public RandomGen 63{ 64 65 public: 66 67 /** 68 * Create a DRAM address sequence generator. 69 * | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed here under. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 51 unchanged lines hidden (view full) --- 62class DramGen : public RandomGen 63{ 64 65 public: 66 67 /** 68 * Create a DRAM address sequence generator. 69 * |
70 * @param _name Name to use for status and debug 71 * @param master_id MasterID set on each request | 70 * @param gen Traffic generator owning this sequence generator |
72 * @param _duration duration of this state before transitioning 73 * @param start_addr Start address 74 * @param end_addr End address 75 * @param _blocksize Size used for transactions injected 76 * @param min_period Lower limit of random inter-transaction time 77 * @param max_period Upper limit of random inter-transaction time 78 * @param read_percent Percent of transactions that are reads 79 * @param data_limit Upper limit on how much data to read/write 80 * @param num_seq_pkts Number of packets per stride, each of _blocksize 81 * @param page_size Page size (bytes) used in the DRAM 82 * @param nbr_of_banks_DRAM Total number of banks in DRAM 83 * @param nbr_of_banks_util Number of banks to utilized, 84 * for N banks, we will use banks: 0->(N-1) 85 * @param addr_mapping Address mapping to be used, 86 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo 87 * assumes single channel system 88 */ | 71 * @param _duration duration of this state before transitioning 72 * @param start_addr Start address 73 * @param end_addr End address 74 * @param _blocksize Size used for transactions injected 75 * @param min_period Lower limit of random inter-transaction time 76 * @param max_period Upper limit of random inter-transaction time 77 * @param read_percent Percent of transactions that are reads 78 * @param data_limit Upper limit on how much data to read/write 79 * @param num_seq_pkts Number of packets per stride, each of _blocksize 80 * @param page_size Page size (bytes) used in the DRAM 81 * @param nbr_of_banks_DRAM Total number of banks in DRAM 82 * @param nbr_of_banks_util Number of banks to utilized, 83 * for N banks, we will use banks: 0->(N-1) 84 * @param addr_mapping Address mapping to be used, 85 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo 86 * assumes single channel system 87 */ |
89 DramGen(const std::string& _name, MasterID master_id, Tick _duration, | 88 DramGen(BaseTrafficGen &gen, Tick _duration, |
90 Addr start_addr, Addr end_addr, Addr _blocksize, 91 Tick min_period, Tick max_period, 92 uint8_t read_percent, Addr data_limit, 93 unsigned int num_seq_pkts, unsigned int page_size, 94 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, 95 unsigned int addr_mapping, | 89 Addr start_addr, Addr end_addr, Addr _blocksize, 90 Tick min_period, Tick max_period, 91 uint8_t read_percent, Addr data_limit, 92 unsigned int num_seq_pkts, unsigned int page_size, 93 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, 94 unsigned int addr_mapping, |
96 unsigned int nbr_of_ranks) 97 : RandomGen(_name, master_id, _duration, start_addr, end_addr, 98 _blocksize, min_period, max_period, read_percent, data_limit), 99 numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0), 100 isRead(true), pageSize(page_size), 101 pageBits(floorLog2(page_size / _blocksize)), 102 bankBits(floorLog2(nbr_of_banks_DRAM)), 103 blockBits(floorLog2(_blocksize)), 104 nbrOfBanksDRAM(nbr_of_banks_DRAM), 105 nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping), 106 rankBits(floorLog2(nbr_of_ranks)), 107 nbrOfRanks(nbr_of_ranks) 108 { 109 if (addrMapping != 1 && addrMapping != 0) { 110 addrMapping = 1; 111 warn("Unknown address mapping specified, using RoRaBaCoCh\n"); 112 } 113 } | 95 unsigned int nbr_of_ranks); |
114 115 PacketPtr getNextPacket(); 116 117 /** Insert bank, rank, and column bits into packed 118 * address to create address for 1st command in a 119 * series 120 * @param new_bank Bank number of next packet series 121 * @param new_rank Rank value of next packet series --- 47 unchanged lines hidden --- | 96 97 PacketPtr getNextPacket(); 98 99 /** Insert bank, rank, and column bits into packed 100 * address to create address for 1st command in a 101 * series 102 * @param new_bank Bank number of next packet series 103 * @param new_rank Rank value of next packet series --- 47 unchanged lines hidden --- |