1/*
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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62class DramGen : public RandomGen
63{
64
65 public:
66
67 /**
68 * Create a DRAM address sequence generator.
69 *
70 * @param obj SimObject owning this sequence generator
71 * @param master_id MasterID related to the memory requests
72 * @param _duration duration of this state before transitioning
73 * @param start_addr Start address
74 * @param end_addr End address
75 * @param _blocksize Size used for transactions injected
76 * @param cacheline_size cache line size in the system
77 * @param min_period Lower limit of random inter-transaction time
78 * @param max_period Upper limit of random inter-transaction time
79 * @param read_percent Percent of transactions that are reads
80 * @param data_limit Upper limit on how much data to read/write
81 * @param num_seq_pkts Number of packets per stride, each of _blocksize
82 * @param page_size Page size (bytes) used in the DRAM
83 * @param nbr_of_banks_DRAM Total number of banks in DRAM
84 * @param nbr_of_banks_util Number of banks to utilized,
85 * for N banks, we will use banks: 0->(N-1)
86 * @param addr_mapping Address mapping to be used,
87 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
88 * assumes single channel system
89 */
90 DramGen(SimObject &obj,
91 MasterID master_id, Tick _duration,
92 Addr start_addr, Addr end_addr,
93 Addr _blocksize, Addr cacheline_size,
94 Tick min_period, Tick max_period,
95 uint8_t read_percent, Addr data_limit,
96 unsigned int num_seq_pkts, unsigned int page_size,
97 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
98 unsigned int addr_mapping,
99 unsigned int nbr_of_ranks);
100
101 PacketPtr getNextPacket();

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