1/*
2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44
45#include <algorithm>
46
47#include "base/random.hh"
48#include "base/trace.hh"
49#include "debug/TrafficGen.hh"
50
51
52DramGen::DramGen(SimObject &obj,
53 MasterID master_id, Tick _duration,
54 Addr start_addr, Addr end_addr,
55 Addr _blocksize, Addr cacheline_size,
56 Tick min_period, Tick max_period,
57 uint8_t read_percent, Addr data_limit,
58 unsigned int num_seq_pkts, unsigned int page_size,
59 unsigned int nbr_of_banks_DRAM,
60 unsigned int nbr_of_banks_util,
61 unsigned int addr_mapping,
62 unsigned int nbr_of_ranks)
63 : RandomGen(obj, master_id, _duration, start_addr, end_addr,
64 _blocksize, cacheline_size, min_period, max_period,
65 read_percent, data_limit),
66 numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
67 isRead(true), pageSize(page_size),
68 pageBits(floorLog2(page_size / _blocksize)),
69 bankBits(floorLog2(nbr_of_banks_DRAM)),
70 blockBits(floorLog2(_blocksize)),
71 nbrOfBanksDRAM(nbr_of_banks_DRAM),
72 nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping),
73 rankBits(floorLog2(nbr_of_ranks)),

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