1/* 2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 56 unchanged lines hidden (view full) --- 65 protected: 66 67 /** Name to use for status and debug printing */ 68 const std::string _name; 69 70 /** The MasterID used for generating requests */ 71 const MasterID masterID; 72 |
73 /** 74 * Generate a new request and associated packet 75 * 76 * @param addr Physical address to use 77 * @param size Size of the request 78 * @param cmd Memory command to send 79 * @param flags Optional request flags 80 */ 81 PacketPtr getPacket(Addr addr, unsigned size, const MemCmd& cmd, 82 Request::FlagsType flags = 0); 83 84 public: 85 86 /** Time to spend in this state */ 87 const Tick duration; 88 89 /** 90 * Create a base generator. 91 * |
92 * @param obj simobject owning the generator |
93 * @param master_id MasterID set on each request 94 * @param _duration duration of this state before transitioning 95 */ |
96 BaseGen(SimObject &obj, MasterID master_id, Tick _duration); |
97 98 virtual ~BaseGen() { } 99 100 /** 101 * Get the name, useful for DPRINTFs. 102 * 103 * @return the given name 104 */ --- 27 unchanged lines hidden (view full) --- 132 */ 133 virtual Tick nextPacketTick(bool elastic, Tick delay) const = 0; 134 135}; 136 137class StochasticGen : public BaseGen 138{ 139 public: |
140 StochasticGen(SimObject &obj, 141 MasterID master_id, Tick _duration, 142 Addr start_addr, Addr end_addr, 143 Addr _blocksize, Addr cacheline_size, |
144 Tick min_period, Tick max_period, 145 uint8_t read_percent, Addr data_limit); 146 147 protected: 148 /** Start of address range */ 149 const Addr startAddr; 150 151 /** End of address range */ 152 const Addr endAddr; 153 154 /** Blocksize and address increment */ 155 const Addr blocksize; 156 |
157 /** Cache line size in the simulated system */ 158 const Addr cacheLineSize; 159 |
160 /** Request generation period */ 161 const Tick minPeriod; 162 const Tick maxPeriod; 163 164 /** 165 * Percent of generated transactions that should be reads 166 */ 167 const uint8_t readPercent; 168 169 /** Maximum amount of data to manipulate */ 170 const Addr dataLimit; 171}; 172 173#endif |