1/*
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed here under. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 * Sascha Bischoff
40 * Neha Agarwal
41 */
42
43/**
44 * @file
45 * Declaration of the base generator class for all generators.
46 */
47
48#ifndef __CPU_TRAFFIC_GEN_BASE_GEN_HH__
49#define __CPU_TRAFFIC_GEN_BASE_GEN_HH__
50
51#include "base/bitfield.hh"
52#include "base/intmath.hh"
53#include "mem/packet.hh"
54
55class BaseTrafficGen;
56
57/**
58 * Base class for all generators, with the shared functionality and
59 * virtual functions for entering, executing and leaving the
60 * generator.
61 */
62class BaseGen
63{
64
65 protected:
66
67 /** Name to use for status and debug printing */
68 const std::string _name;
69
70 /** The MasterID used for generating requests */
71 const MasterID masterID;
72
| 1/*
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed here under. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 * Sascha Bischoff
40 * Neha Agarwal
41 */
42
43/**
44 * @file
45 * Declaration of the base generator class for all generators.
46 */
47
48#ifndef __CPU_TRAFFIC_GEN_BASE_GEN_HH__
49#define __CPU_TRAFFIC_GEN_BASE_GEN_HH__
50
51#include "base/bitfield.hh"
52#include "base/intmath.hh"
53#include "mem/packet.hh"
54
55class BaseTrafficGen;
56
57/**
58 * Base class for all generators, with the shared functionality and
59 * virtual functions for entering, executing and leaving the
60 * generator.
61 */
62class BaseGen
63{
64
65 protected:
66
67 /** Name to use for status and debug printing */
68 const std::string _name;
69
70 /** The MasterID used for generating requests */
71 const MasterID masterID;
72
|
73 /** Cache line size in the simulated system */
74 const Addr cacheLineSize;
75
| |
76 /**
77 * Generate a new request and associated packet
78 *
79 * @param addr Physical address to use
80 * @param size Size of the request
81 * @param cmd Memory command to send
82 * @param flags Optional request flags
83 */
84 PacketPtr getPacket(Addr addr, unsigned size, const MemCmd& cmd,
85 Request::FlagsType flags = 0);
86
87 public:
88
89 /** Time to spend in this state */
90 const Tick duration;
91
92 /**
93 * Create a base generator.
94 *
| 73 /**
74 * Generate a new request and associated packet
75 *
76 * @param addr Physical address to use
77 * @param size Size of the request
78 * @param cmd Memory command to send
79 * @param flags Optional request flags
80 */
81 PacketPtr getPacket(Addr addr, unsigned size, const MemCmd& cmd,
82 Request::FlagsType flags = 0);
83
84 public:
85
86 /** Time to spend in this state */
87 const Tick duration;
88
89 /**
90 * Create a base generator.
91 *
|
95 * @param _name Name to use for status and debug
| 92 * @param obj simobject owning the generator
|
96 * @param master_id MasterID set on each request
97 * @param _duration duration of this state before transitioning
98 */
| 93 * @param master_id MasterID set on each request
94 * @param _duration duration of this state before transitioning
95 */
|
99 BaseGen(BaseTrafficGen &gen, Tick _duration);
| 96 BaseGen(SimObject &obj, MasterID master_id, Tick _duration);
|
100
101 virtual ~BaseGen() { }
102
103 /**
104 * Get the name, useful for DPRINTFs.
105 *
106 * @return the given name
107 */
108 std::string name() const { return _name; }
109
110 /**
111 * Enter this generator state.
112 */
113 virtual void enter() = 0;
114
115 /**
116 * Get the next generated packet.
117 *
118 * @return A packet to be sent at the current tick
119 */
120 virtual PacketPtr getNextPacket() = 0;
121
122 /**
123 * Exit this generator state. By default do nothing.
124 */
125 virtual void exit() { };
126
127 /**
128 * Determine the tick when the next packet is available. MaxTick
129 * means that there will not be any further packets in the current
130 * activation cycle of the generator.
131 *
132 * @param elastic should the injection respond to flow control or not
133 * @param delay time the previous packet spent waiting
134 * @return next tick when a packet is available
135 */
136 virtual Tick nextPacketTick(bool elastic, Tick delay) const = 0;
137
138};
139
140class StochasticGen : public BaseGen
141{
142 public:
| 97
98 virtual ~BaseGen() { }
99
100 /**
101 * Get the name, useful for DPRINTFs.
102 *
103 * @return the given name
104 */
105 std::string name() const { return _name; }
106
107 /**
108 * Enter this generator state.
109 */
110 virtual void enter() = 0;
111
112 /**
113 * Get the next generated packet.
114 *
115 * @return A packet to be sent at the current tick
116 */
117 virtual PacketPtr getNextPacket() = 0;
118
119 /**
120 * Exit this generator state. By default do nothing.
121 */
122 virtual void exit() { };
123
124 /**
125 * Determine the tick when the next packet is available. MaxTick
126 * means that there will not be any further packets in the current
127 * activation cycle of the generator.
128 *
129 * @param elastic should the injection respond to flow control or not
130 * @param delay time the previous packet spent waiting
131 * @return next tick when a packet is available
132 */
133 virtual Tick nextPacketTick(bool elastic, Tick delay) const = 0;
134
135};
136
137class StochasticGen : public BaseGen
138{
139 public:
|
143 StochasticGen(BaseTrafficGen &gen, Tick _duration,
144 Addr start_addr, Addr end_addr, Addr _blocksize,
| 140 StochasticGen(SimObject &obj,
141 MasterID master_id, Tick _duration,
142 Addr start_addr, Addr end_addr,
143 Addr _blocksize, Addr cacheline_size,
|
145 Tick min_period, Tick max_period,
146 uint8_t read_percent, Addr data_limit);
147
148 protected:
149 /** Start of address range */
150 const Addr startAddr;
151
152 /** End of address range */
153 const Addr endAddr;
154
155 /** Blocksize and address increment */
156 const Addr blocksize;
157
| 144 Tick min_period, Tick max_period,
145 uint8_t read_percent, Addr data_limit);
146
147 protected:
148 /** Start of address range */
149 const Addr startAddr;
150
151 /** End of address range */
152 const Addr endAddr;
153
154 /** Blocksize and address increment */
155 const Addr blocksize;
156
|
| 157 /** Cache line size in the simulated system */
158 const Addr cacheLineSize;
159
|
158 /** Request generation period */
159 const Tick minPeriod;
160 const Tick maxPeriod;
161
162 /**
163 * Percent of generated transactions that should be reads
164 */
165 const uint8_t readPercent;
166
167 /** Maximum amount of data to manipulate */
168 const Addr dataLimit;
169};
170
171#endif
| 160 /** Request generation period */
161 const Tick minPeriod;
162 const Tick maxPeriod;
163
164 /**
165 * Percent of generated transactions that should be reads
166 */
167 const uint8_t readPercent;
168
169 /** Maximum amount of data to manipulate */
170 const Addr dataLimit;
171};
172
173#endif
|