1/* 2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 32 unchanged lines hidden (view full) --- 41 42#ifndef __CPU_TRAFFIC_GEN_BASE_HH__ 43#define __CPU_TRAFFIC_GEN_BASE_HH__ 44 45#include <memory> 46#include <tuple> 47 48#include "base/statistics.hh" |
49#include "mem/qport.hh" |
50#include "sim/clocked_object.hh" |
51 52class BaseGen; 53class StreamGen; 54class System; 55struct BaseTrafficGenParams; 56 57/** 58 * The traffic generator is a master module that generates stimuli for 59 * the memory system, based on a collection of simple generator 60 * behaviours that are either probabilistic or based on traces. It can 61 * be used stand alone for creating test cases for interconnect and 62 * memory controllers, or function as a black box replacement for 63 * system components that are not yet modelled in detail, e.g. a video 64 * engine or baseband subsystem. 65 */ |
66class BaseTrafficGen : public ClockedObject |
67{ 68 friend class BaseGen; 69 70 protected: // Params 71 /** 72 * The system used to determine which mode we are currently operating 73 * in. 74 */ --- 182 unchanged lines hidden --- |