1/* 2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 50 unchanged lines hidden (view full) --- 59 * behaviours that are either probabilistic or based on traces. It can 60 * be used stand alone for creating test cases for interconnect and 61 * memory controllers, or function as a black box replacement for 62 * system components that are not yet modelled in detail, e.g. a video 63 * engine or baseband subsystem. 64 */ 65class BaseTrafficGen : public MemObject 66{ |
67 friend class BaseGen; 68 |
69 protected: // Params 70 /** 71 * The system used to determine which mode we are currently operating 72 * in. 73 */ 74 System *const system; 75 76 /** --- 111 unchanged lines hidden (view full) --- 188 DrainState drain() override; 189 190 void serialize(CheckpointOut &cp) const override; 191 void unserialize(CheckpointIn &cp) override; 192 193 /** Register statistics */ 194 void regStats() override; 195 |
196 public: // Generator factory methods 197 std::shared_ptr<BaseGen> createIdle(Tick duration); 198 std::shared_ptr<BaseGen> createExit(Tick duration); 199 200 std::shared_ptr<BaseGen> createLinear( 201 Tick duration, 202 Addr start_addr, Addr end_addr, Addr blocksize, 203 Tick min_period, Tick max_period, 204 uint8_t read_percent, Addr data_limit); 205 206 std::shared_ptr<BaseGen> createRandom( 207 Tick duration, 208 Addr start_addr, Addr end_addr, Addr blocksize, 209 Tick min_period, Tick max_period, 210 uint8_t read_percent, Addr data_limit); 211 212 std::shared_ptr<BaseGen> createDram( 213 Tick duration, 214 Addr start_addr, Addr end_addr, Addr blocksize, 215 Tick min_period, Tick max_period, 216 uint8_t read_percent, Addr data_limit, 217 unsigned int num_seq_pkts, unsigned int page_size, 218 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, 219 unsigned int addr_mapping, 220 unsigned int nbr_of_ranks); 221 222 std::shared_ptr<BaseGen> createDramRot( 223 Tick duration, 224 Addr start_addr, Addr end_addr, Addr blocksize, 225 Tick min_period, Tick max_period, 226 uint8_t read_percent, Addr data_limit, 227 unsigned int num_seq_pkts, unsigned int page_size, 228 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, 229 unsigned int addr_mapping, 230 unsigned int nbr_of_ranks, 231 unsigned int max_seq_count_per_rank); 232 233 std::shared_ptr<BaseGen> createTrace( 234 Tick duration, 235 const std::string& trace_file, Addr addr_offset); 236 |
237 protected: 238 void start(); 239 240 virtual std::shared_ptr<BaseGen> nextGenerator() = 0; 241 242 /** 243 * MasterID used in generated requests. 244 */ 245 const MasterID masterID; 246 247 /** Currently active generator */ 248 std::shared_ptr<BaseGen> activeGenerator; 249}; 250 251#endif //__CPU_TRAFFIC_GEN_BASE_HH__ |