1/*
2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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59 * behaviours that are either probabilistic or based on traces. It can
60 * be used stand alone for creating test cases for interconnect and
61 * memory controllers, or function as a black box replacement for
62 * system components that are not yet modelled in detail, e.g. a video
63 * engine or baseband subsystem.
64 */
65class BaseTrafficGen : public MemObject
66{
67 protected: // Params
68 /**
69 * The system used to determine which mode we are currently operating
70 * in.
71 */
72 System *const system;
73
74 /**

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186 DrainState drain() override;
187
188 void serialize(CheckpointOut &cp) const override;
189 void unserialize(CheckpointIn &cp) override;
190
191 /** Register statistics */
192 void regStats() override;
193
194 protected:
195 void start();
196
197 virtual std::shared_ptr<BaseGen> nextGenerator() = 0;
198
199 /**
200 * MasterID used in generated requests.
201 */
202 const MasterID masterID;
203
204 /** Currently active generator */
205 std::shared_ptr<BaseGen> activeGenerator;
206};
207
208#endif //__CPU_TRAFFIC_GEN_BASE_HH__