1/*
2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39 * Sascha Bischoff
40 */
41#include "cpu/testers/traffic_gen/base.hh"
42
43#include <sstream>
44
45#include "base/intmath.hh"
46#include "base/random.hh"
47#include "cpu/testers/traffic_gen/base_gen.hh"
48#include "debug/Checkpoint.hh"
49#include "debug/TrafficGen.hh"
50#include "params/BaseTrafficGen.hh"
51#include "sim/sim_exit.hh"
52#include "sim/stats.hh"
53#include "sim/system.hh"
54
55using namespace std;
56
57BaseTrafficGen::BaseTrafficGen(const BaseTrafficGenParams* p)
58 : MemObject(p),
59 system(p->system),
60 elasticReq(p->elastic_req),
61 progressCheck(p->progress_check),
62 noProgressEvent([this]{ noProgress(); }, name()),

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292 .name(name() + ".numRetries")
293 .desc("Number of retries");
294
295 retryTicks
296 .name(name() + ".retryTicks")
297 .desc("Time spent waiting due to back-pressure (ticks)");
298}
299
300bool
301BaseTrafficGen::TrafficGenPort::recvTimingResp(PacketPtr pkt)
302{
303 delete pkt;
304
305 return true;
306}