1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 14 unchanged lines hidden (view full) --- 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28from m5.params import * 29from m5.proxy import * 30 |
31from m5.objects.ClockedObject import ClockedObject |
32 |
33class RubyTester(ClockedObject): |
34 type = 'RubyTester' 35 cxx_header = "cpu/testers/rubytest/RubyTester.hh" 36 num_cpus = Param.Int("number of cpus / RubyPorts") 37 cpuInstDataPort = VectorMasterPort("cpu combo ports to inst & data caches") 38 cpuInstPort = VectorMasterPort("cpu ports to only inst caches") 39 cpuDataPort = VectorMasterPort("cpu ports to only data caches") 40 checks_to_complete = Param.Int(100, "checks to complete") 41 deadlock_threshold = Param.Int(50000, "how often to check for deadlock") 42 wakeup_frequency = Param.Int(10, "number of cycles between wakeups") 43 check_flush = Param.Bool(False, "check cache flushing") 44 system = Param.System(Parent.any, "System we belong to") |