37,38c37,39
< cpuDataPort = VectorMasterPort("the cpu data cache ports")
< cpuInstPort = VectorMasterPort("the cpu inst cache ports")
---
> cpuInstDataPort = VectorMasterPort("cpu combo ports to inst & data caches")
> cpuInstPort = VectorMasterPort("cpu ports to only inst caches")
> cpuDataPort = VectorMasterPort("cpu ports to only data caches")