1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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29from MemObject import MemObject
30from m5.params import *
31from m5.proxy import *
32
33class RubyTester(MemObject):
34 type = 'RubyTester'
35 cxx_header = "cpu/testers/rubytest/RubyTester.hh"
36 num_cpus = Param.Int("number of cpus / RubyPorts")
37 cpuDataPort = VectorMasterPort("the cpu data cache ports")
38 cpuInstPort = VectorMasterPort("the cpu inst cache ports")
39 checks_to_complete = Param.Int(100, "checks to complete")
40 deadlock_threshold = Param.Int(50000, "how often to check for deadlock")
41 wakeup_frequency = Param.Int(10, "number of cycles between wakeups")
42 check_flush = Param.Bool(False, "check cache flushing")
43 system = Param.System(Parent.any, "System we belong to")