1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__
43#define __CPU_RUBYTEST_RUBYTESTER_HH__
44
45#include <iostream>
46#include <string>
47#include <vector>
48
49#include "cpu/testers/rubytest/CheckTable.hh"
50#include "mem/ruby/common/Global.hh"
51#include "mem/ruby/common/SubBlock.hh"
52#include "mem/ruby/system/RubyPort.hh"
53#include "mem/mem_object.hh"
54#include "mem/packet.hh"
55#include "params/RubyTester.hh"
56
57class RubyTester : public MemObject
58{
59 public:
60 class CpuPort : public MasterPort
61 {
62 private:
63 RubyTester *tester;
64
65 public:
66 //
67 // Currently, each instatiation of the RubyTester::CpuPort supports
68 // only instruction or data requests, not both. However, for those
69 // RubyPorts that support both types of requests, separate InstOnly
70 // and DataOnly CpuPorts will map to that RubyPort
71
72 CpuPort(const std::string &_name, RubyTester *_tester, PortID _id)
73 : MasterPort(_name, _tester, _id), tester(_tester)
74 {}
75
76 protected:
77 virtual bool recvTimingResp(PacketPtr pkt);
78 virtual void recvRetry()
79 { panic("%s does not expect a retry\n", name()); }
80 };
81
82 struct SenderState : public Packet::SenderState
83 {
84 SubBlock subBlock;
85
86 SenderState(Address addr, int size) : subBlock(addr, size) {}
87
88 };
89
90 typedef RubyTesterParams Params;
91 RubyTester(const Params *p);
92 ~RubyTester();
93
94 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
95 PortID idx = InvalidPortID);
96
97 bool isInstReadableCpuPort(int idx);
98
99 MasterPort* getReadableCpuPort(int idx);
100 MasterPort* getWritableCpuPort(int idx);
101
102 virtual void init();
103
104 void wakeup();
105
106 void incrementCheckCompletions() { m_checks_completed++; }
107
108 void printStats(std::ostream& out) const {}
109 void clearStats() {}
110 void printConfig(std::ostream& out) const {}
111
112 void print(std::ostream& out) const;
113 bool getCheckFlush() { return m_check_flush; }
114
115 MasterID masterId() { return _masterId; }
116 protected:
117 class CheckStartEvent : public Event
118 {
119 private:
120 RubyTester *tester;
121
122 public:
123 CheckStartEvent(RubyTester *_tester)
124 : Event(CPU_Tick_Pri), tester(_tester)
125 {}
126 void process() { tester->wakeup(); }
127 virtual const char *description() const { return "RubyTester tick"; }
128 };
129
130 CheckStartEvent checkStartEvent;
131
132 MasterID _masterId;
133
134 private:
135 void hitCallback(NodeID proc, SubBlock* data);
136
137 void checkForDeadlock();
138
139 // Private copy constructor and assignment operator
140 RubyTester(const RubyTester& obj);
141 RubyTester& operator=(const RubyTester& obj);
142
143 CheckTable* m_checkTable_ptr;
| 1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__
43#define __CPU_RUBYTEST_RUBYTESTER_HH__
44
45#include <iostream>
46#include <string>
47#include <vector>
48
49#include "cpu/testers/rubytest/CheckTable.hh"
50#include "mem/ruby/common/Global.hh"
51#include "mem/ruby/common/SubBlock.hh"
52#include "mem/ruby/system/RubyPort.hh"
53#include "mem/mem_object.hh"
54#include "mem/packet.hh"
55#include "params/RubyTester.hh"
56
57class RubyTester : public MemObject
58{
59 public:
60 class CpuPort : public MasterPort
61 {
62 private:
63 RubyTester *tester;
64
65 public:
66 //
67 // Currently, each instatiation of the RubyTester::CpuPort supports
68 // only instruction or data requests, not both. However, for those
69 // RubyPorts that support both types of requests, separate InstOnly
70 // and DataOnly CpuPorts will map to that RubyPort
71
72 CpuPort(const std::string &_name, RubyTester *_tester, PortID _id)
73 : MasterPort(_name, _tester, _id), tester(_tester)
74 {}
75
76 protected:
77 virtual bool recvTimingResp(PacketPtr pkt);
78 virtual void recvRetry()
79 { panic("%s does not expect a retry\n", name()); }
80 };
81
82 struct SenderState : public Packet::SenderState
83 {
84 SubBlock subBlock;
85
86 SenderState(Address addr, int size) : subBlock(addr, size) {}
87
88 };
89
90 typedef RubyTesterParams Params;
91 RubyTester(const Params *p);
92 ~RubyTester();
93
94 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
95 PortID idx = InvalidPortID);
96
97 bool isInstReadableCpuPort(int idx);
98
99 MasterPort* getReadableCpuPort(int idx);
100 MasterPort* getWritableCpuPort(int idx);
101
102 virtual void init();
103
104 void wakeup();
105
106 void incrementCheckCompletions() { m_checks_completed++; }
107
108 void printStats(std::ostream& out) const {}
109 void clearStats() {}
110 void printConfig(std::ostream& out) const {}
111
112 void print(std::ostream& out) const;
113 bool getCheckFlush() { return m_check_flush; }
114
115 MasterID masterId() { return _masterId; }
116 protected:
117 class CheckStartEvent : public Event
118 {
119 private:
120 RubyTester *tester;
121
122 public:
123 CheckStartEvent(RubyTester *_tester)
124 : Event(CPU_Tick_Pri), tester(_tester)
125 {}
126 void process() { tester->wakeup(); }
127 virtual const char *description() const { return "RubyTester tick"; }
128 };
129
130 CheckStartEvent checkStartEvent;
131
132 MasterID _masterId;
133
134 private:
135 void hitCallback(NodeID proc, SubBlock* data);
136
137 void checkForDeadlock();
138
139 // Private copy constructor and assignment operator
140 RubyTester(const RubyTester& obj);
141 RubyTester& operator=(const RubyTester& obj);
142
143 CheckTable* m_checkTable_ptr;
|