1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__
43#define __CPU_RUBYTEST_RUBYTESTER_HH__
44
45#include <iostream>
46#include <string>
47#include <vector>
48
49#include "cpu/testers/rubytest/CheckTable.hh"
50#include "mem/mem_object.hh"
51#include "mem/packet.hh"
52#include "mem/ruby/common/SubBlock.hh"
53#include "mem/ruby/common/TypeDefines.hh"
54#include "params/RubyTester.hh"
55
56class RubyTester : public MemObject
57{
58 public:
59 class CpuPort : public MasterPort
60 {
61 private:
62 RubyTester *tester;
63 // index for m_last_progress_vector and hitCallback
64 PortID globalIdx;
65
66 public:
67 //
68 // Currently, each instatiation of the RubyTester::CpuPort supports
69 // only instruction or data requests, not both. However, for those
70 // RubyPorts that support both types of requests, separate InstOnly
71 // and DataOnly CpuPorts will map to that RubyPort
72
73 CpuPort(const std::string &_name, RubyTester *_tester, PortID _id,
74 PortID _index)
75 : MasterPort(_name, _tester, _id), tester(_tester),
76 globalIdx(_index)
77 {}
78
79 protected:
80 virtual bool recvTimingResp(PacketPtr pkt);
81 virtual void recvReqRetry()
82 { panic("%s does not expect a retry\n", name()); }
83 };
84
85 struct SenderState : public Packet::SenderState
86 {
87 SubBlock subBlock;
88
89 SenderState(Addr addr, int size) : subBlock(addr, size) {}
90
91 };
92
93 typedef RubyTesterParams Params;
94 RubyTester(const Params *p);
95 ~RubyTester();
96
97 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
98 PortID idx = InvalidPortID);
99
100 bool isInstOnlyCpuPort(int idx);
101 bool isInstDataCpuPort(int idx);
102
103 MasterPort* getReadableCpuPort(int idx);
104 MasterPort* getWritableCpuPort(int idx);
105
106 virtual void init();
107
108 void wakeup();
109
110 void incrementCheckCompletions() { m_checks_completed++; }
111
112 void printStats(std::ostream& out) const {}
113 void clearStats() {}
114 void printConfig(std::ostream& out) const {}
115
116 void print(std::ostream& out) const;
117 bool getCheckFlush() { return m_check_flush; }
118
119 MasterID masterId() { return _masterId; }
120 protected:
| 1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__
43#define __CPU_RUBYTEST_RUBYTESTER_HH__
44
45#include <iostream>
46#include <string>
47#include <vector>
48
49#include "cpu/testers/rubytest/CheckTable.hh"
50#include "mem/mem_object.hh"
51#include "mem/packet.hh"
52#include "mem/ruby/common/SubBlock.hh"
53#include "mem/ruby/common/TypeDefines.hh"
54#include "params/RubyTester.hh"
55
56class RubyTester : public MemObject
57{
58 public:
59 class CpuPort : public MasterPort
60 {
61 private:
62 RubyTester *tester;
63 // index for m_last_progress_vector and hitCallback
64 PortID globalIdx;
65
66 public:
67 //
68 // Currently, each instatiation of the RubyTester::CpuPort supports
69 // only instruction or data requests, not both. However, for those
70 // RubyPorts that support both types of requests, separate InstOnly
71 // and DataOnly CpuPorts will map to that RubyPort
72
73 CpuPort(const std::string &_name, RubyTester *_tester, PortID _id,
74 PortID _index)
75 : MasterPort(_name, _tester, _id), tester(_tester),
76 globalIdx(_index)
77 {}
78
79 protected:
80 virtual bool recvTimingResp(PacketPtr pkt);
81 virtual void recvReqRetry()
82 { panic("%s does not expect a retry\n", name()); }
83 };
84
85 struct SenderState : public Packet::SenderState
86 {
87 SubBlock subBlock;
88
89 SenderState(Addr addr, int size) : subBlock(addr, size) {}
90
91 };
92
93 typedef RubyTesterParams Params;
94 RubyTester(const Params *p);
95 ~RubyTester();
96
97 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
98 PortID idx = InvalidPortID);
99
100 bool isInstOnlyCpuPort(int idx);
101 bool isInstDataCpuPort(int idx);
102
103 MasterPort* getReadableCpuPort(int idx);
104 MasterPort* getWritableCpuPort(int idx);
105
106 virtual void init();
107
108 void wakeup();
109
110 void incrementCheckCompletions() { m_checks_completed++; }
111
112 void printStats(std::ostream& out) const {}
113 void clearStats() {}
114 void printConfig(std::ostream& out) const {}
115
116 void print(std::ostream& out) const;
117 bool getCheckFlush() { return m_check_flush; }
118
119 MasterID masterId() { return _masterId; }
120 protected:
|