RubyTester.cc (8922:17f037ad8918) RubyTester.cc (8932:1b2c17565ac8)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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48#include "mem/ruby/eventqueue/RubyEventQueue.hh"
49#include "mem/ruby/system/System.hh"
50#include "sim/sim_exit.hh"
51#include "sim/system.hh"
52
53RubyTester::RubyTester(const Params *p)
54 : MemObject(p), checkStartEvent(this),
55 _masterId(p->system->getMasterId(name())),
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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48#include "mem/ruby/eventqueue/RubyEventQueue.hh"
49#include "mem/ruby/system/System.hh"
50#include "sim/sim_exit.hh"
51#include "sim/system.hh"
52
53RubyTester::RubyTester(const Params *p)
54 : MemObject(p), checkStartEvent(this),
55 _masterId(p->system->getMasterId(name())),
56 m_num_cpus(p->num_cpus),
56 m_checks_to_complete(p->checks_to_complete),
57 m_deadlock_threshold(p->deadlock_threshold),
58 m_wakeup_frequency(p->wakeup_frequency),
57 m_checks_to_complete(p->checks_to_complete),
58 m_deadlock_threshold(p->deadlock_threshold),
59 m_wakeup_frequency(p->wakeup_frequency),
59 m_check_flush(p->check_flush)
60 m_check_flush(p->check_flush),
61 m_num_inst_ports(p->port_cpuInstPort_connection_count)
60{
61 m_checks_completed = 0;
62
62{
63 m_checks_completed = 0;
64
63 // create the ports
64 for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
65 ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
66 this, i));
65 //
66 // Create the requested inst and data ports and place them on the
67 // appropriate read and write port lists. The reason for the subtle
68 // difference between inst and data ports vs. read and write ports is
69 // from the tester's perspective, it only needs to know whether a port
70 // supports reads (checks) or writes (actions). Meanwhile, the protocol
71 // controllers have data ports (support read and writes) or inst ports
72 // (support only reads).
73 // Note: the inst ports are the lowest elements of the readPort vector,
74 // then the data ports are added to the readPort vector
75 //
76 for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
77 readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
78 this, i,
79 RubyTester::CpuPort::InstOnly));
67 }
80 }
81 for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
82 CpuPort *port = NULL;
83 port = new CpuPort(csprintf("%s-dataPort%d", name(), i), this, i,
84 RubyTester::CpuPort::DataOnly);
85 readPorts.push_back(port);
86 writePorts.push_back(port);
87 }
68
69 // add the check start event to the event queue
70 schedule(checkStartEvent, 1);
71}
72
73RubyTester::~RubyTester()
74{
75 delete m_checkTable_ptr;
88
89 // add the check start event to the event queue
90 schedule(checkStartEvent, 1);
91}
92
93RubyTester::~RubyTester()
94{
95 delete m_checkTable_ptr;
76 for (int i = 0; i < ports.size(); i++)
77 delete ports[i];
96 // Only delete the readPorts since the writePorts are just a subset
97 for (int i = 0; i < readPorts.size(); i++)
98 delete readPorts[i];
78}
79
80void
81RubyTester::init()
82{
99}
100
101void
102RubyTester::init()
103{
83 assert(ports.size() > 0);
104 assert(writePorts.size() > 0 && readPorts.size() > 0);
84
105
85 m_last_progress_vector.resize(ports.size());
106 m_last_progress_vector.resize(m_num_cpus);
86 for (int i = 0; i < m_last_progress_vector.size(); i++) {
87 m_last_progress_vector[i] = 0;
88 }
89
107 for (int i = 0; i < m_last_progress_vector.size(); i++) {
108 m_last_progress_vector[i] = 0;
109 }
110
90 m_num_cpu_sequencers = ports.size();
111 m_num_writers = writePorts.size();
112 m_num_readers = readPorts.size();
91
113
92 m_checkTable_ptr = new CheckTable(m_num_cpu_sequencers, this);
114 m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
93}
94
95MasterPort &
96RubyTester::getMasterPort(const std::string &if_name, int idx)
97{
115}
116
117MasterPort &
118RubyTester::getMasterPort(const std::string &if_name, int idx)
119{
98 if (if_name != "cpuPort") {
120 if (if_name != "cpuInstPort" && if_name != "cpuDataPort") {
99 // pass it along to our super class
100 return MemObject::getMasterPort(if_name, idx);
101 } else {
121 // pass it along to our super class
122 return MemObject::getMasterPort(if_name, idx);
123 } else {
102 if (idx >= static_cast<int>(ports.size())) {
103 panic("RubyTester::getMasterPort: unknown index %d\n", idx);
124 if (if_name == "cpuInstPort") {
125 printf("print getting inst port %d\n", idx);
126 if (idx > m_num_inst_ports) {
127 panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
128 idx);
129 }
130 //
131 // inst ports directly map to the lowest readPort elements
132 //
133 return *readPorts[idx];
134 } else {
135 assert(if_name == "cpuDataPort");
136 //
137 // add the inst port offset to translate to the correct read port
138 // index
139 //
140 int read_idx = idx + m_num_inst_ports;
141 if (read_idx >= static_cast<int>(readPorts.size())) {
142 panic("RubyTester::getMasterPort: unknown data port idx %d\n",
143 idx);
144 }
145 return *readPorts[read_idx];
104 }
146 }
105
106 return *ports[idx];
107 }
108}
109
110Tick
111RubyTester::CpuPort::recvAtomic(PacketPtr pkt)
112{
113 panic("RubyTester::CpuPort::recvAtomic() not implemented!\n");
114 return 0;

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132 // (includes sublock) and the packet, then return
133 delete senderState;
134 delete pkt->req;
135 delete pkt;
136 return true;
137}
138
139MasterPort*
147 }
148}
149
150Tick
151RubyTester::CpuPort::recvAtomic(PacketPtr pkt)
152{
153 panic("RubyTester::CpuPort::recvAtomic() not implemented!\n");
154 return 0;

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172 // (includes sublock) and the packet, then return
173 delete senderState;
174 delete pkt->req;
175 delete pkt;
176 return true;
177}
178
179MasterPort*
140RubyTester::getCpuPort(int idx)
180RubyTester::getReadableCpuPort(int idx)
141{
181{
142 assert(idx >= 0 && idx < ports.size());
182 assert(idx >= 0 && idx < readPorts.size());
143
183
144 return ports[idx];
184 return readPorts[idx];
145}
146
185}
186
187MasterPort*
188RubyTester::getWritableCpuPort(int idx)
189{
190 assert(idx >= 0 && idx < writePorts.size());
191
192 return writePorts[idx];
193}
194
147void
148RubyTester::hitCallback(NodeID proc, SubBlock* data)
149{
150 // Mark that we made progress
151 m_last_progress_vector[proc] = g_eventQueue_ptr->getTime();
152
153 DPRINTF(RubyTest, "completed request for proc: %d\n", proc);
154 DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ",

--- 57 unchanged lines hidden --- 		195void
196RubyTester::hitCallback(NodeID proc, SubBlock* data)
197{
198 // Mark that we made progress
199 m_last_progress_vector[proc] = g_eventQueue_ptr->getTime();
200
201 DPRINTF(RubyTest, "completed request for proc: %d\n", proc);
202 DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ",

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