1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 61 unchanged lines hidden (view full) --- 70 // supports reads (checks) or writes (actions). Meanwhile, the protocol 71 // controllers have data ports (support read and writes) or inst ports 72 // (support only reads). 73 // Note: the inst ports are the lowest elements of the readPort vector, 74 // then the data ports are added to the readPort vector 75 // 76 for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) { 77 readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i), |
78 this, i)); |
79 } 80 for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) { |
81 CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i), 82 this, i); |
83 readPorts.push_back(port); 84 writePorts.push_back(port); 85 } 86 87 // add the check start event to the event queue 88 schedule(checkStartEvent, 1); 89} 90 --- 70 unchanged lines hidden (view full) --- 161 // Now that the tester has completed, delete the senderState 162 // (includes sublock) and the packet, then return 163 delete senderState; 164 delete pkt->req; 165 delete pkt; 166 return true; 167} 168 |
169bool 170RubyTester::isInstReadableCpuPort(int idx) 171{ 172 return idx < m_num_inst_ports; 173} 174 |
175MasterPort* 176RubyTester::getReadableCpuPort(int idx) 177{ 178 assert(idx >= 0 && idx < readPorts.size()); 179 180 return readPorts[idx]; 181} 182 --- 73 unchanged lines hidden --- |