1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "base/misc.hh"
43#include "cpu/testers/rubytest/Check.hh"
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/RubyTest.hh"
46#include "mem/ruby/common/Global.hh"
47#include "mem/ruby/common/SubBlock.hh"
48#include "mem/ruby/system/System.hh"
49#include "sim/sim_exit.hh"
50#include "sim/system.hh"
51
52RubyTester::RubyTester(const Params *p)
53 : MemObject(p), checkStartEvent(this),
54 _masterId(p->system->getMasterId(name())),
55 m_num_cpus(p->num_cpus),
56 m_checks_to_complete(p->checks_to_complete),
57 m_deadlock_threshold(p->deadlock_threshold),
58 m_wakeup_frequency(p->wakeup_frequency),
59 m_check_flush(p->check_flush),
60 m_num_inst_ports(p->port_cpuInstPort_connection_count)
61{
62 m_checks_completed = 0;
63
64 //
65 // Create the requested inst and data ports and place them on the
66 // appropriate read and write port lists. The reason for the subtle
67 // difference between inst and data ports vs. read and write ports is
68 // from the tester's perspective, it only needs to know whether a port
69 // supports reads (checks) or writes (actions). Meanwhile, the protocol
70 // controllers have data ports (support read and writes) or inst ports
71 // (support only reads).
72 // Note: the inst ports are the lowest elements of the readPort vector,
73 // then the data ports are added to the readPort vector
74 //
75 for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
76 readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
77 this, i));
78 }
79 for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
80 CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i),
81 this, i);
82 readPorts.push_back(port);
83 writePorts.push_back(port);
84 }
85
86 // add the check start event to the event queue
87 schedule(checkStartEvent, 1);
88}
89
90RubyTester::~RubyTester()
91{
92 delete m_checkTable_ptr;
93 // Only delete the readPorts since the writePorts are just a subset
94 for (int i = 0; i < readPorts.size(); i++)
95 delete readPorts[i];
96}
97
98void
99RubyTester::init()
100{
101 assert(writePorts.size() > 0 && readPorts.size() > 0);
102
103 m_last_progress_vector.resize(m_num_cpus);
104 for (int i = 0; i < m_last_progress_vector.size(); i++) {
105 m_last_progress_vector[i] = 0;
106 }
107
108 m_num_writers = writePorts.size();
109 m_num_readers = readPorts.size();
110
111 m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
112}
113
114BaseMasterPort &
115RubyTester::getMasterPort(const std::string &if_name, PortID idx)
116{
117 if (if_name != "cpuInstPort" && if_name != "cpuDataPort") {
118 // pass it along to our super class
119 return MemObject::getMasterPort(if_name, idx);
120 } else {
121 if (if_name == "cpuInstPort") {
122 if (idx > m_num_inst_ports) {
123 panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
124 idx);
125 }
126 //
127 // inst ports directly map to the lowest readPort elements
128 //
129 return *readPorts[idx];
130 } else {
131 assert(if_name == "cpuDataPort");
132 //
133 // add the inst port offset to translate to the correct read port
134 // index
135 //
136 int read_idx = idx + m_num_inst_ports;
137 if (read_idx >= static_cast<PortID>(readPorts.size())) {
138 panic("RubyTester::getMasterPort: unknown data port idx %d\n",
139 idx);
140 }
141 return *readPorts[read_idx];
142 }
143 }
144}
145
146bool
147RubyTester::CpuPort::recvTimingResp(PacketPtr pkt)
148{
149 // retrieve the subblock and call hitCallback
150 RubyTester::SenderState* senderState =
151 safe_cast<RubyTester::SenderState*>(pkt->senderState);
152 SubBlock* subblock = senderState->subBlock;
153 assert(subblock != NULL);
154
155 // pop the sender state from the packet
156 pkt->senderState = senderState->saved;
157
158 tester->hitCallback(id, subblock);
159
160 // Now that the tester has completed, delete the senderState
161 // (includes sublock) and the packet, then return
162 delete senderState;
163 delete pkt->req;
164 delete pkt;
165 return true;
166}
167
168bool
169RubyTester::isInstReadableCpuPort(int idx)
170{
171 return idx < m_num_inst_ports;
172}
173
174MasterPort*
175RubyTester::getReadableCpuPort(int idx)
176{
177 assert(idx >= 0 && idx < readPorts.size());
178
179 return readPorts[idx];
180}
181
182MasterPort*
183RubyTester::getWritableCpuPort(int idx)
184{
185 assert(idx >= 0 && idx < writePorts.size());
186
187 return writePorts[idx];
188}
189
190void
191RubyTester::hitCallback(NodeID proc, SubBlock* data)
192{
193 // Mark that we made progress
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "base/misc.hh"
43#include "cpu/testers/rubytest/Check.hh"
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/RubyTest.hh"
46#include "mem/ruby/common/Global.hh"
47#include "mem/ruby/common/SubBlock.hh"
48#include "mem/ruby/system/System.hh"
49#include "sim/sim_exit.hh"
50#include "sim/system.hh"
51
52RubyTester::RubyTester(const Params *p)
53 : MemObject(p), checkStartEvent(this),
54 _masterId(p->system->getMasterId(name())),
55 m_num_cpus(p->num_cpus),
56 m_checks_to_complete(p->checks_to_complete),
57 m_deadlock_threshold(p->deadlock_threshold),
58 m_wakeup_frequency(p->wakeup_frequency),
59 m_check_flush(p->check_flush),
60 m_num_inst_ports(p->port_cpuInstPort_connection_count)
61{
62 m_checks_completed = 0;
63
64 //
65 // Create the requested inst and data ports and place them on the
66 // appropriate read and write port lists. The reason for the subtle
67 // difference between inst and data ports vs. read and write ports is
68 // from the tester's perspective, it only needs to know whether a port
69 // supports reads (checks) or writes (actions). Meanwhile, the protocol
70 // controllers have data ports (support read and writes) or inst ports
71 // (support only reads).
72 // Note: the inst ports are the lowest elements of the readPort vector,
73 // then the data ports are added to the readPort vector
74 //
75 for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
76 readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
77 this, i));
78 }
79 for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
80 CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i),
81 this, i);
82 readPorts.push_back(port);
83 writePorts.push_back(port);
84 }
85
86 // add the check start event to the event queue
87 schedule(checkStartEvent, 1);
88}
89
90RubyTester::~RubyTester()
91{
92 delete m_checkTable_ptr;
93 // Only delete the readPorts since the writePorts are just a subset
94 for (int i = 0; i < readPorts.size(); i++)
95 delete readPorts[i];
96}
97
98void
99RubyTester::init()
100{
101 assert(writePorts.size() > 0 && readPorts.size() > 0);
102
103 m_last_progress_vector.resize(m_num_cpus);
104 for (int i = 0; i < m_last_progress_vector.size(); i++) {
105 m_last_progress_vector[i] = 0;
106 }
107
108 m_num_writers = writePorts.size();
109 m_num_readers = readPorts.size();
110
111 m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
112}
113
114BaseMasterPort &
115RubyTester::getMasterPort(const std::string &if_name, PortID idx)
116{
117 if (if_name != "cpuInstPort" && if_name != "cpuDataPort") {
118 // pass it along to our super class
119 return MemObject::getMasterPort(if_name, idx);
120 } else {
121 if (if_name == "cpuInstPort") {
122 if (idx > m_num_inst_ports) {
123 panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
124 idx);
125 }
126 //
127 // inst ports directly map to the lowest readPort elements
128 //
129 return *readPorts[idx];
130 } else {
131 assert(if_name == "cpuDataPort");
132 //
133 // add the inst port offset to translate to the correct read port
134 // index
135 //
136 int read_idx = idx + m_num_inst_ports;
137 if (read_idx >= static_cast<PortID>(readPorts.size())) {
138 panic("RubyTester::getMasterPort: unknown data port idx %d\n",
139 idx);
140 }
141 return *readPorts[read_idx];
142 }
143 }
144}
145
146bool
147RubyTester::CpuPort::recvTimingResp(PacketPtr pkt)
148{
149 // retrieve the subblock and call hitCallback
150 RubyTester::SenderState* senderState =
151 safe_cast<RubyTester::SenderState*>(pkt->senderState);
152 SubBlock* subblock = senderState->subBlock;
153 assert(subblock != NULL);
154
155 // pop the sender state from the packet
156 pkt->senderState = senderState->saved;
157
158 tester->hitCallback(id, subblock);
159
160 // Now that the tester has completed, delete the senderState
161 // (includes sublock) and the packet, then return
162 delete senderState;
163 delete pkt->req;
164 delete pkt;
165 return true;
166}
167
168bool
169RubyTester::isInstReadableCpuPort(int idx)
170{
171 return idx < m_num_inst_ports;
172}
173
174MasterPort*
175RubyTester::getReadableCpuPort(int idx)
176{
177 assert(idx >= 0 && idx < readPorts.size());
178
179 return readPorts[idx];
180}
181
182MasterPort*
183RubyTester::getWritableCpuPort(int idx)
184{
185 assert(idx >= 0 && idx < writePorts.size());
186
187 return writePorts[idx];
188}
189
190void
191RubyTester::hitCallback(NodeID proc, SubBlock* data)
192{
193 // Mark that we made progress
|
195
196 DPRINTF(RubyTest, "completed request for proc: %d\n", proc);
197 DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ",
198 data->getAddress(), data->getSize());
199 for (int byte = 0; byte < data->getSize(); byte++) {
200 DPRINTF(RubyTest, "%d", data->getByte(byte));
201 }
202 DPRINTF(RubyTest, "\n");
203
204 // This tells us our store has 'completed' or for a load gives us
205 // back the data to make the check
206 Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
207 assert(check_ptr != NULL);
| 195
196 DPRINTF(RubyTest, "completed request for proc: %d\n", proc);
197 DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ",
198 data->getAddress(), data->getSize());
199 for (int byte = 0; byte < data->getSize(); byte++) {
200 DPRINTF(RubyTest, "%d", data->getByte(byte));
201 }
202 DPRINTF(RubyTest, "\n");
203
204 // This tells us our store has 'completed' or for a load gives us
205 // back the data to make the check
206 Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
207 assert(check_ptr != NULL);
|