RubyTester.cc (8941:a47fd7c2d44e) RubyTester.cc (8948:e95ee70f876c)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "base/misc.hh"
43#include "cpu/testers/rubytest/Check.hh"
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/RubyTest.hh"
46#include "mem/ruby/common/Global.hh"
47#include "mem/ruby/common/SubBlock.hh"
48#include "mem/ruby/eventqueue/RubyEventQueue.hh"
49#include "mem/ruby/system/System.hh"
50#include "sim/sim_exit.hh"
51#include "sim/system.hh"
52
53RubyTester::RubyTester(const Params *p)
54 : MemObject(p), checkStartEvent(this),
55 _masterId(p->system->getMasterId(name())),
56 m_num_cpus(p->num_cpus),
57 m_checks_to_complete(p->checks_to_complete),
58 m_deadlock_threshold(p->deadlock_threshold),
59 m_wakeup_frequency(p->wakeup_frequency),
60 m_check_flush(p->check_flush),
61 m_num_inst_ports(p->port_cpuInstPort_connection_count)
62{
63 m_checks_completed = 0;
64
65 //
66 // Create the requested inst and data ports and place them on the
67 // appropriate read and write port lists. The reason for the subtle
68 // difference between inst and data ports vs. read and write ports is
69 // from the tester's perspective, it only needs to know whether a port
70 // supports reads (checks) or writes (actions). Meanwhile, the protocol
71 // controllers have data ports (support read and writes) or inst ports
72 // (support only reads).
73 // Note: the inst ports are the lowest elements of the readPort vector,
74 // then the data ports are added to the readPort vector
75 //
76 for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
77 readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
78 this, i,
79 RubyTester::CpuPort::InstOnly));
80 }
81 for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
82 CpuPort *port = NULL;
83 port = new CpuPort(csprintf("%s-dataPort%d", name(), i), this, i,
84 RubyTester::CpuPort::DataOnly);
85 readPorts.push_back(port);
86 writePorts.push_back(port);
87 }
88
89 // add the check start event to the event queue
90 schedule(checkStartEvent, 1);
91}
92
93RubyTester::~RubyTester()
94{
95 delete m_checkTable_ptr;
96 // Only delete the readPorts since the writePorts are just a subset
97 for (int i = 0; i < readPorts.size(); i++)
98 delete readPorts[i];
99}
100
101void
102RubyTester::init()
103{
104 assert(writePorts.size() > 0 && readPorts.size() > 0);
105
106 m_last_progress_vector.resize(m_num_cpus);
107 for (int i = 0; i < m_last_progress_vector.size(); i++) {
108 m_last_progress_vector[i] = 0;
109 }
110
111 m_num_writers = writePorts.size();
112 m_num_readers = readPorts.size();
113
114 m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
115}
116
117MasterPort &
118RubyTester::getMasterPort(const std::string &if_name, int idx)
119{
120 if (if_name != "cpuInstPort" && if_name != "cpuDataPort") {
121 // pass it along to our super class
122 return MemObject::getMasterPort(if_name, idx);
123 } else {
124 if (if_name == "cpuInstPort") {
125 if (idx > m_num_inst_ports) {
126 panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
127 idx);
128 }
129 //
130 // inst ports directly map to the lowest readPort elements
131 //
132 return *readPorts[idx];
133 } else {
134 assert(if_name == "cpuDataPort");
135 //
136 // add the inst port offset to translate to the correct read port
137 // index
138 //
139 int read_idx = idx + m_num_inst_ports;
140 if (read_idx >= static_cast<int>(readPorts.size())) {
141 panic("RubyTester::getMasterPort: unknown data port idx %d\n",
142 idx);
143 }
144 return *readPorts[read_idx];
145 }
146 }
147}
148
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "base/misc.hh"
43#include "cpu/testers/rubytest/Check.hh"
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/RubyTest.hh"
46#include "mem/ruby/common/Global.hh"
47#include "mem/ruby/common/SubBlock.hh"
48#include "mem/ruby/eventqueue/RubyEventQueue.hh"
49#include "mem/ruby/system/System.hh"
50#include "sim/sim_exit.hh"
51#include "sim/system.hh"
52
53RubyTester::RubyTester(const Params *p)
54 : MemObject(p), checkStartEvent(this),
55 _masterId(p->system->getMasterId(name())),
56 m_num_cpus(p->num_cpus),
57 m_checks_to_complete(p->checks_to_complete),
58 m_deadlock_threshold(p->deadlock_threshold),
59 m_wakeup_frequency(p->wakeup_frequency),
60 m_check_flush(p->check_flush),
61 m_num_inst_ports(p->port_cpuInstPort_connection_count)
62{
63 m_checks_completed = 0;
64
65 //
66 // Create the requested inst and data ports and place them on the
67 // appropriate read and write port lists. The reason for the subtle
68 // difference between inst and data ports vs. read and write ports is
69 // from the tester's perspective, it only needs to know whether a port
70 // supports reads (checks) or writes (actions). Meanwhile, the protocol
71 // controllers have data ports (support read and writes) or inst ports
72 // (support only reads).
73 // Note: the inst ports are the lowest elements of the readPort vector,
74 // then the data ports are added to the readPort vector
75 //
76 for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
77 readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
78 this, i,
79 RubyTester::CpuPort::InstOnly));
80 }
81 for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
82 CpuPort *port = NULL;
83 port = new CpuPort(csprintf("%s-dataPort%d", name(), i), this, i,
84 RubyTester::CpuPort::DataOnly);
85 readPorts.push_back(port);
86 writePorts.push_back(port);
87 }
88
89 // add the check start event to the event queue
90 schedule(checkStartEvent, 1);
91}
92
93RubyTester::~RubyTester()
94{
95 delete m_checkTable_ptr;
96 // Only delete the readPorts since the writePorts are just a subset
97 for (int i = 0; i < readPorts.size(); i++)
98 delete readPorts[i];
99}
100
101void
102RubyTester::init()
103{
104 assert(writePorts.size() > 0 && readPorts.size() > 0);
105
106 m_last_progress_vector.resize(m_num_cpus);
107 for (int i = 0; i < m_last_progress_vector.size(); i++) {
108 m_last_progress_vector[i] = 0;
109 }
110
111 m_num_writers = writePorts.size();
112 m_num_readers = readPorts.size();
113
114 m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
115}
116
117MasterPort &
118RubyTester::getMasterPort(const std::string &if_name, int idx)
119{
120 if (if_name != "cpuInstPort" && if_name != "cpuDataPort") {
121 // pass it along to our super class
122 return MemObject::getMasterPort(if_name, idx);
123 } else {
124 if (if_name == "cpuInstPort") {
125 if (idx > m_num_inst_ports) {
126 panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
127 idx);
128 }
129 //
130 // inst ports directly map to the lowest readPort elements
131 //
132 return *readPorts[idx];
133 } else {
134 assert(if_name == "cpuDataPort");
135 //
136 // add the inst port offset to translate to the correct read port
137 // index
138 //
139 int read_idx = idx + m_num_inst_ports;
140 if (read_idx >= static_cast<int>(readPorts.size())) {
141 panic("RubyTester::getMasterPort: unknown data port idx %d\n",
142 idx);
143 }
144 return *readPorts[read_idx];
145 }
146 }
147}
148
149Tick
150RubyTester::CpuPort::recvAtomic(PacketPtr pkt)
151{
152 panic("RubyTester::CpuPort::recvAtomic() not implemented!\n");
153 return 0;
154}
155
156bool
157RubyTester::CpuPort::recvTiming(PacketPtr pkt)
158{
159 // retrieve the subblock and call hitCallback
160 RubyTester::SenderState* senderState =
161 safe_cast<RubyTester::SenderState*>(pkt->senderState);
162 SubBlock* subblock = senderState->subBlock;
163 assert(subblock != NULL);
164
165 // pop the sender state from the packet
166 pkt->senderState = senderState->saved;
167
168 tester->hitCallback(idx, subblock);
169
170 // Now that the tester has completed, delete the senderState
171 // (includes sublock) and the packet, then return
172 delete senderState;
173 delete pkt->req;
174 delete pkt;
175 return true;
176}
177
178MasterPort*
179RubyTester::getReadableCpuPort(int idx)
180{
181 assert(idx >= 0 && idx < readPorts.size());
182
183 return readPorts[idx];
184}
185
186MasterPort*
187RubyTester::getWritableCpuPort(int idx)
188{
189 assert(idx >= 0 && idx < writePorts.size());
190
191 return writePorts[idx];
192}
193
194void
195RubyTester::hitCallback(NodeID proc, SubBlock* data)
196{
197 // Mark that we made progress
198 m_last_progress_vector[proc] = g_eventQueue_ptr->getTime();
199
200 DPRINTF(RubyTest, "completed request for proc: %d\n", proc);
201 DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ",
202 data->getAddress(), data->getSize());
203 for (int byte = 0; byte < data->getSize(); byte++) {
204 DPRINTF(RubyTest, "%d", data->getByte(byte));
205 }
206 DPRINTF(RubyTest, "\n");
207
208 // This tells us our store has 'completed' or for a load gives us
209 // back the data to make the check
210 Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
211 assert(check_ptr != NULL);
212 check_ptr->performCallback(proc, data);
213}
214
215void
216RubyTester::wakeup()
217{
218 if (m_checks_completed < m_checks_to_complete) {
219 // Try to perform an action or check
220 Check* check_ptr = m_checkTable_ptr->getRandomCheck();
221 assert(check_ptr != NULL);
222 check_ptr->initiate();
223
224 checkForDeadlock();
225
226 schedule(checkStartEvent, curTick() + m_wakeup_frequency);
227 } else {
228 exitSimLoop("Ruby Tester completed");
229 }
230}
231
232void
233RubyTester::checkForDeadlock()
234{
235 int size = m_last_progress_vector.size();
236 Time current_time = g_eventQueue_ptr->getTime();
237 for (int processor = 0; processor < size; processor++) {
238 if ((current_time - m_last_progress_vector[processor]) >
239 m_deadlock_threshold) {
240 panic("Deadlock detected: current_time: %d last_progress_time: %d "
241 "difference: %d processor: %d\n",
242 current_time, m_last_progress_vector[processor],
243 current_time - m_last_progress_vector[processor], processor);
244 }
245 }
246}
247
248void
249RubyTester::print(std::ostream& out) const
250{
251 out << "[RubyTester]" << std::endl;
252}
253
254RubyTester *
255RubyTesterParams::create()
256{
257 return new RubyTester(this);
258}
149bool
150RubyTester::CpuPort::recvTiming(PacketPtr pkt)
151{
152 // retrieve the subblock and call hitCallback
153 RubyTester::SenderState* senderState =
154 safe_cast<RubyTester::SenderState*>(pkt->senderState);
155 SubBlock* subblock = senderState->subBlock;
156 assert(subblock != NULL);
157
158 // pop the sender state from the packet
159 pkt->senderState = senderState->saved;
160
161 tester->hitCallback(idx, subblock);
162
163 // Now that the tester has completed, delete the senderState
164 // (includes sublock) and the packet, then return
165 delete senderState;
166 delete pkt->req;
167 delete pkt;
168 return true;
169}
170
171MasterPort*
172RubyTester::getReadableCpuPort(int idx)
173{
174 assert(idx >= 0 && idx < readPorts.size());
175
176 return readPorts[idx];
177}
178
179MasterPort*
180RubyTester::getWritableCpuPort(int idx)
181{
182 assert(idx >= 0 && idx < writePorts.size());
183
184 return writePorts[idx];
185}
186
187void
188RubyTester::hitCallback(NodeID proc, SubBlock* data)
189{
190 // Mark that we made progress
191 m_last_progress_vector[proc] = g_eventQueue_ptr->getTime();
192
193 DPRINTF(RubyTest, "completed request for proc: %d\n", proc);
194 DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ",
195 data->getAddress(), data->getSize());
196 for (int byte = 0; byte < data->getSize(); byte++) {
197 DPRINTF(RubyTest, "%d", data->getByte(byte));
198 }
199 DPRINTF(RubyTest, "\n");
200
201 // This tells us our store has 'completed' or for a load gives us
202 // back the data to make the check
203 Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
204 assert(check_ptr != NULL);
205 check_ptr->performCallback(proc, data);
206}
207
208void
209RubyTester::wakeup()
210{
211 if (m_checks_completed < m_checks_to_complete) {
212 // Try to perform an action or check
213 Check* check_ptr = m_checkTable_ptr->getRandomCheck();
214 assert(check_ptr != NULL);
215 check_ptr->initiate();
216
217 checkForDeadlock();
218
219 schedule(checkStartEvent, curTick() + m_wakeup_frequency);
220 } else {
221 exitSimLoop("Ruby Tester completed");
222 }
223}
224
225void
226RubyTester::checkForDeadlock()
227{
228 int size = m_last_progress_vector.size();
229 Time current_time = g_eventQueue_ptr->getTime();
230 for (int processor = 0; processor < size; processor++) {
231 if ((current_time - m_last_progress_vector[processor]) >
232 m_deadlock_threshold) {
233 panic("Deadlock detected: current_time: %d last_progress_time: %d "
234 "difference: %d processor: %d\n",
235 current_time, m_last_progress_vector[processor],
236 current_time - m_last_progress_vector[processor], processor);
237 }
238 }
239}
240
241void
242RubyTester::print(std::ostream& out) const
243{
244 out << "[RubyTester]" << std::endl;
245}
246
247RubyTester *
248RubyTesterParams::create()
249{
250 return new RubyTester(this);
251}