Check.cc (8832:247fee427324) Check.cc (8932:1b2c17565ac8)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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31#include "debug/RubyTest.hh"
32#include "mem/ruby/common/SubBlock.hh"
33#include "mem/ruby/system/Sequencer.hh"
34#include "mem/ruby/system/System.hh"
35
36typedef RubyTester::SenderState SenderState;
37
38Check::Check(const Address& address, const Address& pc,
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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31#include "debug/RubyTest.hh"
32#include "mem/ruby/common/SubBlock.hh"
33#include "mem/ruby/system/Sequencer.hh"
34#include "mem/ruby/system/System.hh"
35
36typedef RubyTester::SenderState SenderState;
37
38Check::Check(const Address& address, const Address& pc,
39 int _num_cpu_sequencers, RubyTester* _tester)
40 : m_num_cpu_sequencers(_num_cpu_sequencers), m_tester_ptr(_tester)
39 int _num_writers, int _num_readers, RubyTester* _tester)
40 : m_num_writers(_num_writers), m_num_readers(_num_readers),
41 m_tester_ptr(_tester)
41{
42 m_status = TesterStatus_Idle;
43
44 pickValue();
45 pickInitiatingNode();
46 changeAddress(address);
47 m_pc = pc;
48 m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM);

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75 }
76}
77
78void
79Check::initiatePrefetch()
80{
81 DPRINTF(RubyTest, "initiating prefetch\n");
82
42{
43 m_status = TesterStatus_Idle;
44
45 pickValue();
46 pickInitiatingNode();
47 changeAddress(address);
48 m_pc = pc;
49 m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM);

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76 }
77}
78
79void
80Check::initiatePrefetch()
81{
82 DPRINTF(RubyTest, "initiating prefetch\n");
83
83 int index = random() % m_num_cpu_sequencers;
84 int index = random() % m_num_readers;
84 RubyTester::CpuPort* port =
85 RubyTester::CpuPort* port =
85 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
86 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getReadableCpuPort(index));
86
87 Request::Flags flags;
88 flags.set(Request::PREFETCH);
89
90 Packet::Command cmd;
91
92 // 1 in 8 chance this will be an exclusive prefetch
93 if ((random() & 0x7) != 0) {
94 cmd = MemCmd::ReadReq;
95
87
88 Request::Flags flags;
89 flags.set(Request::PREFETCH);
90
91 Packet::Command cmd;
92
93 // 1 in 8 chance this will be an exclusive prefetch
94 if ((random() & 0x7) != 0) {
95 cmd = MemCmd::ReadReq;
96
96 // 50% chance that the request will be an instruction fetch
97 if ((random() & 0x1) == 0) {
97 // if necessary, make the request an instruction fetch
98 if (port->type == RubyTester::CpuPort::InstOnly) {
98 flags.set(Request::INST_FETCH);
99 }
100 } else {
101 cmd = MemCmd::WriteReq;
102 flags.set(Request::PF_EXCLUSIVE);
103 }
104
105 // Prefetches are assumed to be 0 sized

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130}
131
132void
133Check::initiateFlush()
134{
135
136 DPRINTF(RubyTest, "initiating Flush\n");
137
99 flags.set(Request::INST_FETCH);
100 }
101 } else {
102 cmd = MemCmd::WriteReq;
103 flags.set(Request::PF_EXCLUSIVE);
104 }
105
106 // Prefetches are assumed to be 0 sized

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131}
132
133void
134Check::initiateFlush()
135{
136
137 DPRINTF(RubyTest, "initiating Flush\n");
138
138 int index = random() % m_num_cpu_sequencers;
139 int index = random() % m_num_writers;
139 RubyTester::CpuPort* port =
140 RubyTester::CpuPort* port =
140 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
141 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getWritableCpuPort(index));
141
142 Request::Flags flags;
143
144 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
145 m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
146
147 Packet::Command cmd;
148

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161}
162
163void
164Check::initiateAction()
165{
166 DPRINTF(RubyTest, "initiating Action\n");
167 assert(m_status == TesterStatus_Idle);
168
142
143 Request::Flags flags;
144
145 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
146 m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
147
148 Packet::Command cmd;
149

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162}
163
164void
165Check::initiateAction()
166{
167 DPRINTF(RubyTest, "initiating Action\n");
168 assert(m_status == TesterStatus_Idle);
169
169 int index = random() % m_num_cpu_sequencers;
170 int index = random() % m_num_writers;
170 RubyTester::CpuPort* port =
171 RubyTester::CpuPort* port =
171 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
172 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getWritableCpuPort(index));
172
173 Request::Flags flags;
174
175 // Create the particular address for the next byte to be written
176 Address writeAddr(m_address.getAddress() + m_store_count);
177
178 // Stores are assumed to be 1 byte-sized
179 Request *req = new Request(writeAddr.getAddress(), 1, flags,

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226}
227
228void
229Check::initiateCheck()
230{
231 DPRINTF(RubyTest, "Initiating Check\n");
232 assert(m_status == TesterStatus_Ready);
233
173
174 Request::Flags flags;
175
176 // Create the particular address for the next byte to be written
177 Address writeAddr(m_address.getAddress() + m_store_count);
178
179 // Stores are assumed to be 1 byte-sized
180 Request *req = new Request(writeAddr.getAddress(), 1, flags,

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227}
228
229void
230Check::initiateCheck()
231{
232 DPRINTF(RubyTest, "Initiating Check\n");
233 assert(m_status == TesterStatus_Ready);
234
234 int index = random() % m_num_cpu_sequencers;
235 int index = random() % m_num_readers;
235 RubyTester::CpuPort* port =
236 RubyTester::CpuPort* port =
236 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
237 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getReadableCpuPort(index));
237
238 Request::Flags flags;
239
238
239 Request::Flags flags;
240
240 // 50% chance that the request will be an instruction fetch
241 if ((random() & 0x1) == 0) {
241 // If necessary, make the request an instruction fetch
242 if (port->type == RubyTester::CpuPort::InstOnly) {
242 flags.set(Request::INST_FETCH);
243 }
244
245 // Checks are sized depending on the number of bytes written
246 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
247 m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
248
249 req->setThreadContext(index, 0);

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358 m_store_count = 0;
359}
360
361void
362Check::pickInitiatingNode()
363{
364 assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
365 m_status = TesterStatus_Idle;
243 flags.set(Request::INST_FETCH);
244 }
245
246 // Checks are sized depending on the number of bytes written
247 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
248 m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
249
250 req->setThreadContext(index, 0);

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359 m_store_count = 0;
360}
361
362void
363Check::pickInitiatingNode()
364{
365 assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
366 m_status = TesterStatus_Idle;
366 m_initiatingNode = (random() % m_num_cpu_sequencers);
367 m_initiatingNode = (random() % m_num_writers);
367 DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode);
368 m_store_count = 0;
369}
370
371void
372Check::print(std::ostream& out) const
373{
374 out << "["

--- 17 unchanged lines hidden --- 		368 DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode);
369 m_store_count = 0;
370}
371
372void
373Check::print(std::ostream& out) const
374{
375 out << "["

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