Check.cc (8232:b28d06a175be) Check.cc (8832:247fee427324)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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98 flags.set(Request::INST_FETCH);
99 }
100 } else {
101 cmd = MemCmd::WriteReq;
102 flags.set(Request::PF_EXCLUSIVE);
103 }
104
105 // Prefetches are assumed to be 0 sized
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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98 flags.set(Request::INST_FETCH);
99 }
100 } else {
101 cmd = MemCmd::WriteReq;
102 flags.set(Request::PF_EXCLUSIVE);
103 }
104
105 // Prefetches are assumed to be 0 sized
106 Request *req = new Request(m_address.getAddress(), 0, flags, curTick(),
107 m_pc.getAddress());
106 Request *req = new Request(m_address.getAddress(), 0, flags,
107 m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
108 req->setThreadContext(index, 0);
109
110 PacketPtr pkt = new Packet(req, cmd, port->idx);
111
112 // push the subblock onto the sender state. The sequencer will
113 // update the subblock on the return
114 pkt->senderState =
115 new SenderState(m_address, req->getSize(), pkt->senderState);

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136 DPRINTF(RubyTest, "initiating Flush\n");
137
138 int index = random() % m_num_cpu_sequencers;
139 RubyTester::CpuPort* port =
140 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
141
142 Request::Flags flags;
143
108 req->setThreadContext(index, 0);
109
110 PacketPtr pkt = new Packet(req, cmd, port->idx);
111
112 // push the subblock onto the sender state. The sequencer will
113 // update the subblock on the return
114 pkt->senderState =
115 new SenderState(m_address, req->getSize(), pkt->senderState);

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136 DPRINTF(RubyTest, "initiating Flush\n");
137
138 int index = random() % m_num_cpu_sequencers;
139 RubyTester::CpuPort* port =
140 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
141
142 Request::Flags flags;
143
144 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, curTick(),
145 m_pc.getAddress());
144 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
145 m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
146
147 Packet::Command cmd;
148
149 cmd = MemCmd::FlushReq;
150
151 PacketPtr pkt = new Packet(req, cmd, port->idx);
152
153 // push the subblock onto the sender state. The sequencer will

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171 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
172
173 Request::Flags flags;
174
175 // Create the particular address for the next byte to be written
176 Address writeAddr(m_address.getAddress() + m_store_count);
177
178 // Stores are assumed to be 1 byte-sized
146
147 Packet::Command cmd;
148
149 cmd = MemCmd::FlushReq;
150
151 PacketPtr pkt = new Packet(req, cmd, port->idx);
152
153 // push the subblock onto the sender state. The sequencer will

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171 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
172
173 Request::Flags flags;
174
175 // Create the particular address for the next byte to be written
176 Address writeAddr(m_address.getAddress() + m_store_count);
177
178 // Stores are assumed to be 1 byte-sized
179 Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick(),
179 Request *req = new Request(writeAddr.getAddress(), 1, flags,
180 m_tester_ptr->masterId(), curTick(),
180 m_pc.getAddress());
181
182 req->setThreadContext(index, 0);
183 Packet::Command cmd;
184
185 // 1 out of 8 chance, issue an atomic rather than a write
186 // if ((random() & 0x7) == 0) {
187 // cmd = MemCmd::SwapReq;

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238
239 // 50% chance that the request will be an instruction fetch
240 if ((random() & 0x1) == 0) {
241 flags.set(Request::INST_FETCH);
242 }
243
244 // Checks are sized depending on the number of bytes written
245 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
181 m_pc.getAddress());
182
183 req->setThreadContext(index, 0);
184 Packet::Command cmd;
185
186 // 1 out of 8 chance, issue an atomic rather than a write
187 // if ((random() & 0x7) == 0) {
188 // cmd = MemCmd::SwapReq;

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239
240 // 50% chance that the request will be an instruction fetch
241 if ((random() & 0x1) == 0) {
242 flags.set(Request::INST_FETCH);
243 }
244
245 // Checks are sized depending on the number of bytes written
246 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
246 curTick(), m_pc.getAddress());
247 m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
247
248 req->setThreadContext(index, 0);
249 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
250 uint8_t* dataArray = new uint8_t[CHECK_SIZE];
251 pkt->dataDynamicArray(dataArray);
252
253 // push the subblock onto the sender state. The sequencer will
254 // update the subblock on the return

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249 req->setThreadContext(index, 0);
250 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
251 uint8_t* dataArray = new uint8_t[CHECK_SIZE];
252 pkt->dataDynamicArray(dataArray);
253
254 // push the subblock onto the sender state. The sequencer will
255 // update the subblock on the return

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