Check.cc (10302:0e9e99e6369a) | Check.cc (10348:c91b23c72d5e) |
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1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * Copyright (c) 2009 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 | 1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * Copyright (c) 2009 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 |
30#include "base/random.hh" |
|
30#include "cpu/testers/rubytest/Check.hh" 31#include "debug/RubyTest.hh" 32#include "mem/ruby/common/SubBlock.hh" 33#include "mem/ruby/system/Sequencer.hh" 34#include "mem/ruby/system/System.hh" 35 36typedef RubyTester::SenderState SenderState; 37 38Check::Check(const Address& address, const Address& pc, 39 int _num_writers, int _num_readers, RubyTester* _tester) 40 : m_num_writers(_num_writers), m_num_readers(_num_readers), 41 m_tester_ptr(_tester) 42{ 43 m_status = TesterStatus_Idle; 44 45 pickValue(); 46 pickInitiatingNode(); 47 changeAddress(address); 48 m_pc = pc; | 31#include "cpu/testers/rubytest/Check.hh" 32#include "debug/RubyTest.hh" 33#include "mem/ruby/common/SubBlock.hh" 34#include "mem/ruby/system/Sequencer.hh" 35#include "mem/ruby/system/System.hh" 36 37typedef RubyTester::SenderState SenderState; 38 39Check::Check(const Address& address, const Address& pc, 40 int _num_writers, int _num_readers, RubyTester* _tester) 41 : m_num_writers(_num_writers), m_num_readers(_num_readers), 42 m_tester_ptr(_tester) 43{ 44 m_status = TesterStatus_Idle; 45 46 pickValue(); 47 pickInitiatingNode(); 48 changeAddress(address); 49 m_pc = pc; |
49 m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM); | 50 m_access_mode = RubyAccessMode(random_mt.random(0, 51 RubyAccessMode_NUM - 1)); |
50 m_store_count = 0; 51} 52 53void 54Check::initiate() 55{ 56 DPRINTF(RubyTest, "initiating\n"); 57 debugPrint(); 58 59 // currently no protocols support prefetches | 52 m_store_count = 0; 53} 54 55void 56Check::initiate() 57{ 58 DPRINTF(RubyTest, "initiating\n"); 59 debugPrint(); 60 61 // currently no protocols support prefetches |
60 if (false && (random() & 0xf) == 0) { | 62 if (false && (random_mt.random(0, 0xf) == 0)) { |
61 initiatePrefetch(); // Prefetch from random processor 62 } 63 | 63 initiatePrefetch(); // Prefetch from random processor 64 } 65 |
64 if (m_tester_ptr->getCheckFlush() && (random() & 0xff) == 0) { | 66 if (m_tester_ptr->getCheckFlush() && (random_mt.random(0, 0xff) == 0)) { |
65 initiateFlush(); // issue a Flush request from random processor 66 } 67 68 if (m_status == TesterStatus_Idle) { 69 initiateAction(); 70 } else if (m_status == TesterStatus_Ready) { 71 initiateCheck(); 72 } else { 73 // Pending - do nothing 74 DPRINTF(RubyTest, 75 "initiating action/check - failed: action/check is pending\n"); 76 } 77} 78 79void 80Check::initiatePrefetch() 81{ 82 DPRINTF(RubyTest, "initiating prefetch\n"); 83 | 67 initiateFlush(); // issue a Flush request from random processor 68 } 69 70 if (m_status == TesterStatus_Idle) { 71 initiateAction(); 72 } else if (m_status == TesterStatus_Ready) { 73 initiateCheck(); 74 } else { 75 // Pending - do nothing 76 DPRINTF(RubyTest, 77 "initiating action/check - failed: action/check is pending\n"); 78 } 79} 80 81void 82Check::initiatePrefetch() 83{ 84 DPRINTF(RubyTest, "initiating prefetch\n"); 85 |
84 int index = random() % m_num_readers; | 86 int index = random_mt.random(0, m_num_readers - 1); |
85 MasterPort* port = m_tester_ptr->getReadableCpuPort(index); 86 87 Request::Flags flags; 88 flags.set(Request::PREFETCH); 89 90 Packet::Command cmd; 91 92 // 1 in 8 chance this will be an exclusive prefetch | 87 MasterPort* port = m_tester_ptr->getReadableCpuPort(index); 88 89 Request::Flags flags; 90 flags.set(Request::PREFETCH); 91 92 Packet::Command cmd; 93 94 // 1 in 8 chance this will be an exclusive prefetch |
93 if ((random() & 0x7) != 0) { | 95 if (random_mt.random(0, 0x7) != 0) { |
94 cmd = MemCmd::ReadReq; 95 96 // if necessary, make the request an instruction fetch 97 if (m_tester_ptr->isInstReadableCpuPort(index)) { 98 flags.set(Request::INST_FETCH); 99 } 100 } else { 101 cmd = MemCmd::WriteReq; --- 25 unchanged lines hidden (view full) --- 127} 128 129void 130Check::initiateFlush() 131{ 132 133 DPRINTF(RubyTest, "initiating Flush\n"); 134 | 96 cmd = MemCmd::ReadReq; 97 98 // if necessary, make the request an instruction fetch 99 if (m_tester_ptr->isInstReadableCpuPort(index)) { 100 flags.set(Request::INST_FETCH); 101 } 102 } else { 103 cmd = MemCmd::WriteReq; --- 25 unchanged lines hidden (view full) --- 129} 130 131void 132Check::initiateFlush() 133{ 134 135 DPRINTF(RubyTest, "initiating Flush\n"); 136 |
135 int index = random() % m_num_writers; | 137 int index = random_mt.random(0, m_num_writers - 1); |
136 MasterPort* port = m_tester_ptr->getWritableCpuPort(index); 137 138 Request::Flags flags; 139 140 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, 141 m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); 142 143 Packet::Command cmd; --- 12 unchanged lines hidden (view full) --- 156} 157 158void 159Check::initiateAction() 160{ 161 DPRINTF(RubyTest, "initiating Action\n"); 162 assert(m_status == TesterStatus_Idle); 163 | 138 MasterPort* port = m_tester_ptr->getWritableCpuPort(index); 139 140 Request::Flags flags; 141 142 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, 143 m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); 144 145 Packet::Command cmd; --- 12 unchanged lines hidden (view full) --- 158} 159 160void 161Check::initiateAction() 162{ 163 DPRINTF(RubyTest, "initiating Action\n"); 164 assert(m_status == TesterStatus_Idle); 165 |
164 int index = random() % m_num_writers; | 166 int index = random_mt.random(0, m_num_writers - 1); |
165 MasterPort* port = m_tester_ptr->getWritableCpuPort(index); 166 167 Request::Flags flags; 168 169 // Create the particular address for the next byte to be written 170 Address writeAddr(m_address.getAddress() + m_store_count); 171 172 // Stores are assumed to be 1 byte-sized --- 44 unchanged lines hidden (view full) --- 217} 218 219void 220Check::initiateCheck() 221{ 222 DPRINTF(RubyTest, "Initiating Check\n"); 223 assert(m_status == TesterStatus_Ready); 224 | 167 MasterPort* port = m_tester_ptr->getWritableCpuPort(index); 168 169 Request::Flags flags; 170 171 // Create the particular address for the next byte to be written 172 Address writeAddr(m_address.getAddress() + m_store_count); 173 174 // Stores are assumed to be 1 byte-sized --- 44 unchanged lines hidden (view full) --- 219} 220 221void 222Check::initiateCheck() 223{ 224 DPRINTF(RubyTest, "Initiating Check\n"); 225 assert(m_status == TesterStatus_Ready); 226 |
225 int index = random() % m_num_readers; | 227 int index = random_mt.random(0, m_num_readers - 1); |
226 MasterPort* port = m_tester_ptr->getReadableCpuPort(index); 227 228 Request::Flags flags; 229 230 // If necessary, make the request an instruction fetch 231 if (m_tester_ptr->isInstReadableCpuPort(index)) { 232 flags.set(Request::INST_FETCH); 233 } --- 100 unchanged lines hidden (view full) --- 334 m_store_count = 0; 335} 336 337void 338Check::pickValue() 339{ 340 assert(m_status == TesterStatus_Idle); 341 m_status = TesterStatus_Idle; | 228 MasterPort* port = m_tester_ptr->getReadableCpuPort(index); 229 230 Request::Flags flags; 231 232 // If necessary, make the request an instruction fetch 233 if (m_tester_ptr->isInstReadableCpuPort(index)) { 234 flags.set(Request::INST_FETCH); 235 } --- 100 unchanged lines hidden (view full) --- 336 m_store_count = 0; 337} 338 339void 340Check::pickValue() 341{ 342 assert(m_status == TesterStatus_Idle); 343 m_status = TesterStatus_Idle; |
342 m_value = random() & 0xff; // One byte | 344 m_value = random_mt.random(0, 0xff); // One byte |
343 m_store_count = 0; 344} 345 346void 347Check::pickInitiatingNode() 348{ 349 assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 350 m_status = TesterStatus_Idle; | 345 m_store_count = 0; 346} 347 348void 349Check::pickInitiatingNode() 350{ 351 assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 352 m_status = TesterStatus_Idle; |
351 m_initiatingNode = (random() % m_num_writers); | 353 m_initiatingNode = (random_mt.random(0, m_num_writers - 1)); |
352 DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode); 353 m_store_count = 0; 354} 355 356void 357Check::print(std::ostream& out) const 358{ 359 out << "[" --- 17 unchanged lines hidden --- | 354 DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode); 355 m_store_count = 0; 356} 357 358void 359Check::print(std::ostream& out) const 360{ 361 out << "[" --- 17 unchanged lines hidden --- |