memtest.hh (9301:1e8d01c15a77) memtest.hh (10688:22452667fd5c)
1/*
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Andreas Hansson
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
43 */
44
45#ifndef __CPU_MEMTEST_MEMTEST_HH__
46#define __CPU_MEMTEST_MEMTEST_HH__
47
48#include <set>
49#include <unordered_map>
36
37#include "base/statistics.hh"
38#include "mem/mem_object.hh"
50
51#include "base/statistics.hh"
52#include "mem/mem_object.hh"
39#include "mem/port.hh"
40#include "mem/port_proxy.hh"
41#include "params/MemTest.hh"
42#include "sim/eventq.hh"
53#include "params/MemTest.hh"
54#include "sim/eventq.hh"
43#include "sim/sim_exit.hh"
44#include "sim/sim_object.hh"
45#include "sim/stats.hh"
46
55#include "sim/stats.hh"
56
47class Packet;
57/**
58 * The MemTest class tests a cache coherent memory system by
59 * generating false sharing and verifying the read data against a
60 * reference updated on the completion of writes. Each tester reads
61 * and writes a specific byte in a cache line, as determined by its
62 * unique id. Thus, all requests issued by the MemTest instance are a
63 * single byte and a specific address is only ever touched by a single
64 * tester.
65 *
66 * In addition to verifying the data, the tester also has timeouts for
67 * both requests and responses, thus checking that the memory-system
68 * is making progress.
69 */
48class MemTest : public MemObject
49{
70class MemTest : public MemObject
71{
72
50 public:
73 public:
74
51 typedef MemTestParams Params;
52 MemTest(const Params *p);
53
75 typedef MemTestParams Params;
76 MemTest(const Params *p);
77
54 virtual void init();
55
56 // register statistics
57 virtual void regStats();
58
78 virtual void regStats();
79
59 // main simulation loop (one cycle)
60 void tick();
61
62 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
63 PortID idx = InvalidPortID);
64
80 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
81 PortID idx = InvalidPortID);
82
65 /**
66 * Print state of address in memory system via PrintReq (for
67 * debugging).
68 */
69 void printAddr(Addr a);
70
71 protected:
83 protected:
72 class TickEvent : public Event
73 {
74 private:
75 MemTest *cpu;
76
84
77 public:
78 TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
79 void process() { cpu->tick(); }
80 virtual const char *description() const { return "MemTest tick"; }
81 };
85 void tick();
82
86
83 TickEvent tickEvent;
87 EventWrapper<MemTest, &MemTest::tick> tickEvent;
84
88
89 void noRequest();
90
91 EventWrapper<MemTest, &MemTest::noRequest> noRequestEvent;
92
93 void noResponse();
94
95 EventWrapper<MemTest, &MemTest::noResponse> noResponseEvent;
96
85 class CpuPort : public MasterPort
86 {
97 class CpuPort : public MasterPort
98 {
87 MemTest *memtest;
99 MemTest &memtest;
88
89 public:
90
100
101 public:
102
91 CpuPort(const std::string &_name, MemTest *_memtest)
92 : MasterPort(_name, _memtest), memtest(_memtest)
103 CpuPort(const std::string &_name, MemTest &_memtest)
104 : MasterPort(_name, &_memtest), memtest(_memtest)
93 { }
94
95 protected:
96
105 { }
106
107 protected:
108
97 virtual bool recvTimingResp(PacketPtr pkt);
109 bool recvTimingResp(PacketPtr pkt);
98
110
99 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
111 void recvTimingSnoopReq(PacketPtr pkt) { }
100
112
101 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
113 void recvFunctionalSnoop(PacketPtr pkt) { }
102
114
103 virtual void recvFunctionalSnoop(PacketPtr pkt) { }
115 Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
104
116
105 virtual void recvRetry();
117 void recvRetry();
106 };
107
118 };
119
108 CpuPort cachePort;
109 CpuPort funcPort;
110 PortProxy funcProxy;
120 CpuPort port;
111
121
112 class MemTestSenderState : public Packet::SenderState
113 {
114 public:
115 /** Constructor. */
116 MemTestSenderState(uint8_t *_data)
117 : data(_data)
118 { }
119
120 // Hold onto data pointer
121 uint8_t *data;
122 };
123
124 PacketPtr retryPkt;
125
122 PacketPtr retryPkt;
123
126 bool accessRetry;
127
128 //
129 // The dmaOustanding flag enforces only one dma at a time
130 //
131 bool dmaOutstanding;
124 const unsigned size;
132
125
133 unsigned size; // size of testing memory region
126 const Cycles interval;
134
127
135 unsigned percentReads; // target percentage of read accesses
136 unsigned percentFunctional; // target percentage of functional accesses
137 unsigned percentUncacheable;
128 const unsigned percentReads;
129 const unsigned percentFunctional;
130 const unsigned percentUncacheable;
138
131
139 bool issueDmas;
140
141 /** Request id for all generated traffic */
142 MasterID masterId;
143
132 /** Request id for all generated traffic */
133 MasterID masterId;
134
144 int id;
135 unsigned int id;
145
136
146 std::set<unsigned> outstandingAddrs;
137 std::set<Addr> outstandingAddrs;
147
138
148 unsigned blockSize;
139 // store the expected value for the addresses we have touched
140 std::unordered_map<Addr, uint8_t> referenceData;
149
141
150 Addr blockAddrMask;
142 const unsigned blockSize;
151
143
152 Addr blockAddr(Addr addr)
144 const Addr blockAddrMask;
145
146 /**
147 * Get the block aligned address.
148 *
149 * @param addr Address to align
150 * @return The block aligned address
151 */
152 Addr blockAlign(Addr addr) const
153 {
154 return (addr & ~blockAddrMask);
155 }
156
153 {
154 return (addr & ~blockAddrMask);
155 }
156
157 Addr traceBlockAddr;
158
159 Addr baseAddr1; // fix this to option
160 Addr baseAddr2; // fix this to option
157 Addr baseAddr1;
158 Addr baseAddr2;
161 Addr uncacheAddr;
162
159 Addr uncacheAddr;
160
163 unsigned progressInterval; // frequency of progress reports
161 const unsigned progressInterval; // frequency of progress reports
162 const Cycles progressCheck;
164 Tick nextProgressMessage; // access # for next progress report
165
163 Tick nextProgressMessage; // access # for next progress report
164
166 unsigned percentSourceUnaligned;
167 unsigned percentDestUnaligned;
168
169 Tick noResponseCycles;
170
171 uint64_t numReads;
172 uint64_t numWrites;
165 uint64_t numReads;
166 uint64_t numWrites;
173 uint64_t maxLoads;
167 const uint64_t maxLoads;
174
168
175 bool atomic;
176 bool suppress_func_warnings;
169 const bool atomic;
177
170
171 const bool suppressFuncWarnings;
172
178 Stats::Scalar numReadsStat;
179 Stats::Scalar numWritesStat;
173 Stats::Scalar numReadsStat;
174 Stats::Scalar numWritesStat;
180 Stats::Scalar numCopiesStat;
181
175
182 // called by MemCompleteEvent::process()
183 void completeRequest(PacketPtr pkt);
176 /**
177 * Complete a request by checking the response.
178 *
179 * @param pkt Response packet
180 * @param functional Whether the access was functional or not
181 */
182 void completeRequest(PacketPtr pkt, bool functional = false);
184
183
185 void sendPkt(PacketPtr pkt);
184 bool sendPkt(PacketPtr pkt);
186
185
187 void doRetry();
186 void recvRetry();
188
187
189 friend class MemCompleteEvent;
190};
191
192#endif // __CPU_MEMTEST_MEMTEST_HH__
188};
189
190#endif // __CPU_MEMTEST_MEMTEST_HH__