memtest.hh (9157:e0bad9d7bbd6) | memtest.hh (9294:8fb03b13de02) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 45 unchanged lines hidden (view full) --- 54 virtual void init(); 55 56 // register statistics 57 virtual void regStats(); 58 59 // main simulation loop (one cycle) 60 void tick(); 61 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 45 unchanged lines hidden (view full) --- 54 virtual void init(); 55 56 // register statistics 57 virtual void regStats(); 58 59 // main simulation loop (one cycle) 60 void tick(); 61 |
62 virtual MasterPort &getMasterPort(const std::string &if_name, 63 int idx = -1); | 62 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 63 PortID idx = InvalidPortID); |
64 65 /** 66 * Print state of address in memory system via PrintReq (for 67 * debugging). 68 */ 69 void printAddr(Addr a); 70 71 protected: --- 124 unchanged lines hidden --- | 64 65 /** 66 * Print state of address in memory system via PrintReq (for 67 * debugging). 68 */ 69 void printAddr(Addr a); 70 71 protected: --- 124 unchanged lines hidden --- |