memtest.hh (8853:0216ed80991b) memtest.hh (8922:17f037ad8918)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 48 unchanged lines hidden (view full) ---

57 // register statistics
58 virtual void regStats();
59
60 inline Tick ticks(int numCycles) const { return numCycles; }
61
62 // main simulation loop (one cycle)
63 void tick();
64
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 48 unchanged lines hidden (view full) ---

57 // register statistics
58 virtual void regStats();
59
60 inline Tick ticks(int numCycles) const { return numCycles; }
61
62 // main simulation loop (one cycle)
63 void tick();
64
65 virtual Port *getPort(const std::string &if_name, int idx = -1);
65 virtual MasterPort &getMasterPort(const std::string &if_name,
66 int idx = -1);
66
67 /**
68 * Print state of address in memory system via PrintReq (for
69 * debugging).
70 */
71 void printAddr(Addr a);
72
73 protected:

--- 5 unchanged lines hidden (view full) ---

79 public:
80 TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
81 void process() { cpu->tick(); }
82 virtual const char *description() const { return "MemTest tick"; }
83 };
84
85 TickEvent tickEvent;
86
67
68 /**
69 * Print state of address in memory system via PrintReq (for
70 * debugging).
71 */
72 void printAddr(Addr a);
73
74 protected:

--- 5 unchanged lines hidden (view full) ---

80 public:
81 TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
82 void process() { cpu->tick(); }
83 virtual const char *description() const { return "MemTest tick"; }
84 };
85
86 TickEvent tickEvent;
87
87 class CpuPort : public Port
88 class CpuPort : public MasterPort
88 {
89 MemTest *memtest;
90
91 public:
92
93 CpuPort(const std::string &_name, MemTest *_memtest)
89 {
90 MemTest *memtest;
91
92 public:
93
94 CpuPort(const std::string &_name, MemTest *_memtest)
94 : Port(_name, _memtest), memtest(_memtest)
95 : MasterPort(_name, _memtest), memtest(_memtest)
95 { }
96
97 protected:
98
99 virtual bool recvTiming(PacketPtr pkt);
100
101 virtual Tick recvAtomic(PacketPtr pkt);
102
103 virtual void recvFunctional(PacketPtr pkt);
104
96 { }
97
98 protected:
99
100 virtual bool recvTiming(PacketPtr pkt);
101
102 virtual Tick recvAtomic(PacketPtr pkt);
103
104 virtual void recvFunctional(PacketPtr pkt);
105
105 virtual void recvRangeChange();
106
107 virtual void recvRetry();
108 };
109
110 CpuPort cachePort;
111 CpuPort funcPort;
112 PortProxy funcProxy;
113
114 class MemTestSenderState : public Packet::SenderState, public FastAlloc

--- 83 unchanged lines hidden --- 		106 virtual void recvRetry();
107 };
108
109 CpuPort cachePort;
110 CpuPort funcPort;
111 PortProxy funcProxy;
112
113 class MemTestSenderState : public Packet::SenderState, public FastAlloc

--- 83 unchanged lines hidden ---