memtest.hh (10713:eddb533708cb) memtest.hh (12085:de78ea63e0ca)
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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79
80 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
81 PortID idx = InvalidPortID);
82
83 protected:
84
85 void tick();
86
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 70 unchanged lines hidden (view full) ---

79
80 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
81 PortID idx = InvalidPortID);
82
83 protected:
84
85 void tick();
86
87 EventWrapper<MemTest, &MemTest::tick> tickEvent;
87 EventFunctionWrapper tickEvent;
88
89 void noRequest();
90
88
89 void noRequest();
90
91 EventWrapper<MemTest, &MemTest::noRequest> noRequestEvent;
91 EventFunctionWrapper noRequestEvent;
92
93 void noResponse();
94
92
93 void noResponse();
94
95 EventWrapper<MemTest, &MemTest::noResponse> noResponseEvent;
95 EventFunctionWrapper noResponseEvent;
96
97 class CpuPort : public MasterPort
98 {
99 MemTest &memtest;
100
101 public:
102
103 CpuPort(const std::string &_name, MemTest &_memtest)

--- 87 unchanged lines hidden --- 		96
97 class CpuPort : public MasterPort
98 {
99 MemTest &memtest;
100
101 public:
102
103 CpuPort(const std::string &_name, MemTest &_memtest)

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