1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 */ 31 32#ifndef __CPU_MEMTEST_MEMTEST_HH__ 33#define __CPU_MEMTEST_MEMTEST_HH__ 34 35#include <set> 36
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37#include "base/statistics.hh" 38#include "mem/mem_object.hh" 39#include "mem/port.hh" 40#include "mem/port_proxy.hh" 41#include "params/MemTest.hh" 42#include "sim/eventq.hh" 43#include "sim/sim_exit.hh" 44#include "sim/sim_object.hh" 45#include "sim/stats.hh" 46 47class Packet; 48class MemTest : public MemObject 49{ 50 public: 51 typedef MemTestParams Params; 52 MemTest(const Params *p); 53 54 virtual void init(); 55 56 // register statistics 57 virtual void regStats(); 58 59 inline Tick ticks(int numCycles) const { return numCycles; } 60 61 // main simulation loop (one cycle) 62 void tick(); 63 64 virtual MasterPort &getMasterPort(const std::string &if_name, 65 int idx = -1); 66 67 /** 68 * Print state of address in memory system via PrintReq (for 69 * debugging). 70 */ 71 void printAddr(Addr a); 72 73 protected: 74 class TickEvent : public Event 75 { 76 private: 77 MemTest *cpu; 78 79 public: 80 TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {} 81 void process() { cpu->tick(); } 82 virtual const char *description() const { return "MemTest tick"; } 83 }; 84 85 TickEvent tickEvent; 86 87 class CpuPort : public MasterPort 88 { 89 MemTest *memtest; 90 91 public: 92 93 CpuPort(const std::string &_name, MemTest *_memtest) 94 : MasterPort(_name, _memtest), memtest(_memtest) 95 { } 96 97 protected: 98 99 virtual bool recvTimingResp(PacketPtr pkt); 100 101 virtual void recvTimingSnoopReq(PacketPtr pkt) { } 102 103 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } 104 105 virtual void recvFunctionalSnoop(PacketPtr pkt) { } 106 107 virtual void recvRetry(); 108 }; 109 110 CpuPort cachePort; 111 CpuPort funcPort; 112 PortProxy funcProxy; 113
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