1/* 2 * Copyright (c) 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 35 unchanged lines hidden (view full) --- 44 45#ifndef __CPU_MEMTEST_MEMTEST_HH__ 46#define __CPU_MEMTEST_MEMTEST_HH__ 47 48#include <set> 49#include <unordered_map> 50 51#include "base/statistics.hh" |
52#include "mem/port.hh" |
53#include "params/MemTest.hh" |
54#include "sim/clocked_object.hh" |
55#include "sim/eventq.hh" 56#include "sim/stats.hh" 57 58/** 59 * The MemTest class tests a cache coherent memory system by 60 * generating false sharing and verifying the read data against a 61 * reference updated on the completion of writes. Each tester reads 62 * and writes a specific byte in a cache line, as determined by its 63 * unique id. Thus, all requests issued by the MemTest instance are a 64 * single byte and a specific address is only ever touched by a single 65 * tester. 66 * 67 * In addition to verifying the data, the tester also has timeouts for 68 * both requests and responses, thus checking that the memory-system 69 * is making progress. 70 */ |
71class MemTest : public ClockedObject |
72{ 73 74 public: 75 76 typedef MemTestParams Params; 77 MemTest(const Params *p); 78 79 void regStats() override; --- 112 unchanged lines hidden --- |