1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
36
37#include "base/statistics.hh"
38#include "mem/mem_object.hh"
39#include "mem/port.hh"
40#include "mem/port_proxy.hh"
41#include "params/MemTest.hh"
42#include "sim/eventq.hh"
43#include "sim/sim_exit.hh"
44#include "sim/sim_object.hh"
45#include "sim/stats.hh"
46
47class Packet;
48class MemTest : public MemObject
49{
50 public:
51 typedef MemTestParams Params;
52 MemTest(const Params *p);
53
54 virtual void init();
55
56 // register statistics
57 virtual void regStats();
58
59 // main simulation loop (one cycle)
60 void tick();
61
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
36
37#include "base/statistics.hh"
38#include "mem/mem_object.hh"
39#include "mem/port.hh"
40#include "mem/port_proxy.hh"
41#include "params/MemTest.hh"
42#include "sim/eventq.hh"
43#include "sim/sim_exit.hh"
44#include "sim/sim_object.hh"
45#include "sim/stats.hh"
46
47class Packet;
48class MemTest : public MemObject
49{
50 public:
51 typedef MemTestParams Params;
52 MemTest(const Params *p);
53
54 virtual void init();
55
56 // register statistics
57 virtual void regStats();
58
59 // main simulation loop (one cycle)
60 void tick();
61
|
64
65 /**
66 * Print state of address in memory system via PrintReq (for
67 * debugging).
68 */
69 void printAddr(Addr a);
70
71 protected:
72 class TickEvent : public Event
73 {
74 private:
75 MemTest *cpu;
76
77 public:
78 TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
79 void process() { cpu->tick(); }
80 virtual const char *description() const { return "MemTest tick"; }
81 };
82
83 TickEvent tickEvent;
84
85 class CpuPort : public MasterPort
86 {
87 MemTest *memtest;
88
89 public:
90
91 CpuPort(const std::string &_name, MemTest *_memtest)
92 : MasterPort(_name, _memtest), memtest(_memtest)
93 { }
94
95 protected:
96
97 virtual bool recvTimingResp(PacketPtr pkt);
98
99 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
100
101 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
102
103 virtual void recvFunctionalSnoop(PacketPtr pkt) { }
104
105 virtual void recvRetry();
106 };
107
108 CpuPort cachePort;
109 CpuPort funcPort;
110 PortProxy funcProxy;
111
112 class MemTestSenderState : public Packet::SenderState
113 {
114 public:
115 /** Constructor. */
116 MemTestSenderState(uint8_t *_data)
117 : data(_data)
118 { }
119
120 // Hold onto data pointer
121 uint8_t *data;
122 };
123
124 PacketPtr retryPkt;
125
126 bool accessRetry;
127
128 //
129 // The dmaOustanding flag enforces only one dma at a time
130 //
131 bool dmaOutstanding;
132
133 unsigned size; // size of testing memory region
134
135 unsigned percentReads; // target percentage of read accesses
136 unsigned percentFunctional; // target percentage of functional accesses
137 unsigned percentUncacheable;
138
139 bool issueDmas;
140
141 /** Request id for all generated traffic */
142 MasterID masterId;
143
144 int id;
145
146 std::set<unsigned> outstandingAddrs;
147
148 unsigned blockSize;
149
150 Addr blockAddrMask;
151
152 Addr blockAddr(Addr addr)
153 {
154 return (addr & ~blockAddrMask);
155 }
156
157 Addr traceBlockAddr;
158
159 Addr baseAddr1; // fix this to option
160 Addr baseAddr2; // fix this to option
161 Addr uncacheAddr;
162
163 unsigned progressInterval; // frequency of progress reports
164 Tick nextProgressMessage; // access # for next progress report
165
166 unsigned percentSourceUnaligned;
167 unsigned percentDestUnaligned;
168
169 Tick noResponseCycles;
170
171 uint64_t numReads;
172 uint64_t numWrites;
173 uint64_t maxLoads;
174
175 bool atomic;
176 bool suppress_func_warnings;
177
178 Stats::Scalar numReadsStat;
179 Stats::Scalar numWritesStat;
180 Stats::Scalar numCopiesStat;
181
182 // called by MemCompleteEvent::process()
183 void completeRequest(PacketPtr pkt);
184
185 void sendPkt(PacketPtr pkt);
186
187 void doRetry();
188
189 friend class MemCompleteEvent;
190};
191
192#endif // __CPU_MEMTEST_MEMTEST_HH__
193
194
195
| 64
65 /**
66 * Print state of address in memory system via PrintReq (for
67 * debugging).
68 */
69 void printAddr(Addr a);
70
71 protected:
72 class TickEvent : public Event
73 {
74 private:
75 MemTest *cpu;
76
77 public:
78 TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
79 void process() { cpu->tick(); }
80 virtual const char *description() const { return "MemTest tick"; }
81 };
82
83 TickEvent tickEvent;
84
85 class CpuPort : public MasterPort
86 {
87 MemTest *memtest;
88
89 public:
90
91 CpuPort(const std::string &_name, MemTest *_memtest)
92 : MasterPort(_name, _memtest), memtest(_memtest)
93 { }
94
95 protected:
96
97 virtual bool recvTimingResp(PacketPtr pkt);
98
99 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
100
101 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
102
103 virtual void recvFunctionalSnoop(PacketPtr pkt) { }
104
105 virtual void recvRetry();
106 };
107
108 CpuPort cachePort;
109 CpuPort funcPort;
110 PortProxy funcProxy;
111
112 class MemTestSenderState : public Packet::SenderState
113 {
114 public:
115 /** Constructor. */
116 MemTestSenderState(uint8_t *_data)
117 : data(_data)
118 { }
119
120 // Hold onto data pointer
121 uint8_t *data;
122 };
123
124 PacketPtr retryPkt;
125
126 bool accessRetry;
127
128 //
129 // The dmaOustanding flag enforces only one dma at a time
130 //
131 bool dmaOutstanding;
132
133 unsigned size; // size of testing memory region
134
135 unsigned percentReads; // target percentage of read accesses
136 unsigned percentFunctional; // target percentage of functional accesses
137 unsigned percentUncacheable;
138
139 bool issueDmas;
140
141 /** Request id for all generated traffic */
142 MasterID masterId;
143
144 int id;
145
146 std::set<unsigned> outstandingAddrs;
147
148 unsigned blockSize;
149
150 Addr blockAddrMask;
151
152 Addr blockAddr(Addr addr)
153 {
154 return (addr & ~blockAddrMask);
155 }
156
157 Addr traceBlockAddr;
158
159 Addr baseAddr1; // fix this to option
160 Addr baseAddr2; // fix this to option
161 Addr uncacheAddr;
162
163 unsigned progressInterval; // frequency of progress reports
164 Tick nextProgressMessage; // access # for next progress report
165
166 unsigned percentSourceUnaligned;
167 unsigned percentDestUnaligned;
168
169 Tick noResponseCycles;
170
171 uint64_t numReads;
172 uint64_t numWrites;
173 uint64_t maxLoads;
174
175 bool atomic;
176 bool suppress_func_warnings;
177
178 Stats::Scalar numReadsStat;
179 Stats::Scalar numWritesStat;
180 Stats::Scalar numCopiesStat;
181
182 // called by MemCompleteEvent::process()
183 void completeRequest(PacketPtr pkt);
184
185 void sendPkt(PacketPtr pkt);
186
187 void doRetry();
188
189 friend class MemCompleteEvent;
190};
191
192#endif // __CPU_MEMTEST_MEMTEST_HH__
193
194
195
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