1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
36
37#include "base/statistics.hh"
38#include "mem/mem_object.hh"
39#include "mem/port.hh"
40#include "mem/port_proxy.hh"
41#include "params/MemTest.hh"
42#include "sim/eventq.hh"
43#include "sim/sim_exit.hh"
44#include "sim/sim_object.hh"
45#include "sim/stats.hh"
46
47class Packet;
48class MemTest : public MemObject
49{
50 public:
51 typedef MemTestParams Params;
52 MemTest(const Params *p);
53
54 virtual void init();
55
56 // register statistics
57 virtual void regStats();
58
59 inline Tick ticks(int numCycles) const { return numCycles; }
60
61 // main simulation loop (one cycle)
62 void tick();
63
64 virtual MasterPort &getMasterPort(const std::string &if_name,
65 int idx = -1);
66
67 /**
68 * Print state of address in memory system via PrintReq (for
69 * debugging).
70 */
71 void printAddr(Addr a);
72
73 protected:
74 class TickEvent : public Event
75 {
76 private:
77 MemTest *cpu;
78
79 public:
80 TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
81 void process() { cpu->tick(); }
82 virtual const char *description() const { return "MemTest tick"; }
83 };
84
85 TickEvent tickEvent;
86
87 class CpuPort : public MasterPort
88 {
89 MemTest *memtest;
90
91 public:
92
93 CpuPort(const std::string &_name, MemTest *_memtest)
94 : MasterPort(_name, _memtest), memtest(_memtest)
95 { }
96
97 protected:
98
99 virtual bool recvTimingResp(PacketPtr pkt);
100
101 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
102
103 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
104
105 virtual void recvFunctionalSnoop(PacketPtr pkt) { }
106
107 virtual void recvRetry();
108 };
109
110 CpuPort cachePort;
111 CpuPort funcPort;
112 PortProxy funcProxy;
113
114 class MemTestSenderState : public Packet::SenderState
115 {
116 public:
117 /** Constructor. */
118 MemTestSenderState(uint8_t *_data)
119 : data(_data)
120 { }
121
122 // Hold onto data pointer
123 uint8_t *data;
124 };
125
126 PacketPtr retryPkt;
127
128 bool accessRetry;
129
130 //
131 // The dmaOustanding flag enforces only one dma at a time
132 //
133 bool dmaOutstanding;
134
135 unsigned size; // size of testing memory region
136
137 unsigned percentReads; // target percentage of read accesses
138 unsigned percentFunctional; // target percentage of functional accesses
139 unsigned percentUncacheable;
140
141 bool issueDmas;
142
143 /** Request id for all generated traffic */
144 MasterID masterId;
145
146 int id;
147
148 std::set<unsigned> outstandingAddrs;
149
150 unsigned blockSize;
151
152 Addr blockAddrMask;
153
154 Addr blockAddr(Addr addr)
155 {
156 return (addr & ~blockAddrMask);
157 }
158
159 Addr traceBlockAddr;
160
161 Addr baseAddr1; // fix this to option
162 Addr baseAddr2; // fix this to option
163 Addr uncacheAddr;
164
165 unsigned progressInterval; // frequency of progress reports
166 Tick nextProgressMessage; // access # for next progress report
167
168 unsigned percentSourceUnaligned;
169 unsigned percentDestUnaligned;
170
171 Tick noResponseCycles;
172
173 uint64_t numReads;
174 uint64_t numWrites;
175 uint64_t maxLoads;
176
177 bool atomic;
178 bool suppress_func_warnings;
179
180 Stats::Scalar numReadsStat;
181 Stats::Scalar numWritesStat;
182 Stats::Scalar numCopiesStat;
183
184 // called by MemCompleteEvent::process()
185 void completeRequest(PacketPtr pkt);
186
187 void sendPkt(PacketPtr pkt);
188
189 void doRetry();
190
191 friend class MemCompleteEvent;
192};
193
194#endif // __CPU_MEMTEST_MEMTEST_HH__
195
196
197