memtest.cc (9814:7ad2b0186a32) memtest.cc (10348:c91b23c72d5e)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/random.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "debug/MemTest.hh"
43#include "mem/mem_object.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/sim_events.hh"

--- 208 unchanged lines hidden (view full) ---

256 }
257
258 if (accessRetry || (issueDmas && dmaOutstanding)) {
259 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
260 return;
261 }
262
263 //make new request
41#include "base/statistics.hh"
42#include "cpu/testers/memtest/memtest.hh"
43#include "debug/MemTest.hh"
44#include "mem/mem_object.hh"
45#include "mem/packet.hh"
46#include "mem/port.hh"
47#include "mem/request.hh"
48#include "sim/sim_events.hh"

--- 208 unchanged lines hidden (view full) ---

257 }
258
259 if (accessRetry || (issueDmas && dmaOutstanding)) {
260 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
261 return;
262 }
263
264 //make new request
264 unsigned cmd = random() % 100;
265 unsigned offset = random() % size;
266 unsigned base = random() % 2;
267 uint64_t data = random();
268 unsigned access_size = random() % 4;
269 bool uncacheable = (random() % 100) < percentUncacheable;
265 unsigned cmd = random_mt.random(0, 100);
266 unsigned offset = random_mt.random<unsigned>(0, size - 1);
267 unsigned base = random_mt.random(0, 1);
268 uint64_t data = random_mt.random<uint64_t>();
269 unsigned access_size = random_mt.random(0, 3);
270 bool uncacheable = random_mt.random(0, 100) < percentUncacheable;
270
271
271 unsigned dma_access_size = random() % 4;
272 unsigned dma_access_size = random_mt.random(0, 3);
272
273 //If we aren't doing copies, use id as offset, and do a false sharing
274 //mem tester
275 //We can eliminate the lower bits of the offset, and then use the id
276 //to offset within the blks
277 offset = blockAddr(offset);
278 offset += id;
279 access_size = 0;

--- 11 unchanged lines hidden (view full) ---

291
292 // For now we only allow one outstanding request per address
293 // per tester This means we assume CPU does write forwarding
294 // to reads that alias something in the cpu store buffer.
295 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
296 return;
297 }
298
273
274 //If we aren't doing copies, use id as offset, and do a false sharing
275 //mem tester
276 //We can eliminate the lower bits of the offset, and then use the id
277 //to offset within the blks
278 offset = blockAddr(offset);
279 offset += id;
280 access_size = 0;

--- 11 unchanged lines hidden (view full) ---

292
293 // For now we only allow one outstanding request per address
294 // per tester This means we assume CPU does write forwarding
295 // to reads that alias something in the cpu store buffer.
296 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
297 return;
298 }
299
299 bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
300 bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
301 !uncacheable;
300 Request *req = new Request();
301 uint8_t *result = new uint8_t[8];
302
303 if (issueDmas) {
304 paddr &= ~((1 << dma_access_size) - 1);
305 req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
306 req->setThreadContext(id,0);
307 } else {

--- 79 unchanged lines hidden --- 		302 Request *req = new Request();
303 uint8_t *result = new uint8_t[8];
304
305 if (issueDmas) {
306 paddr &= ~((1 << dma_access_size) - 1);
307 req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
308 req->setThreadContext(id,0);
309 } else {

--- 79 unchanged lines hidden ---