memtest.cc (9180:ee8d7a51651d) | memtest.cc (9294:8fb03b13de02) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 numReads = 0; 127 numWrites = 0; 128 schedule(tickEvent, 0); 129 130 accessRetry = false; 131 dmaOutstanding = false; 132} 133 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 numReads = 0; 127 numWrites = 0; 128 schedule(tickEvent, 0); 129 130 accessRetry = false; 131 dmaOutstanding = false; 132} 133 |
134MasterPort & 135MemTest::getMasterPort(const std::string &if_name, int idx) | 134BaseMasterPort & 135MemTest::getMasterPort(const std::string &if_name, PortID idx) |
136{ 137 if (if_name == "functional") 138 return funcPort; 139 else if (if_name == "test") 140 return cachePort; 141 else 142 return MemObject::getMasterPort(if_name, idx); 143} --- 257 unchanged lines hidden --- | 136{ 137 if (if_name == "functional") 138 return funcPort; 139 else if (if_name == "test") 140 return cachePort; 141 else 142 return MemObject::getMasterPort(if_name, idx); 143} --- 257 unchanged lines hidden --- |