memtest.cc (9179:666bc9df1e49) | memtest.cc (9180:ee8d7a51651d) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 232 unchanged lines hidden (view full) --- 241 .desc("number of copy accesses completed") 242 ; 243} 244 245void 246MemTest::tick() 247{ 248 if (!tickEvent.scheduled()) | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 232 unchanged lines hidden (view full) --- 241 .desc("number of copy accesses completed") 242 ; 243} 244 245void 246MemTest::tick() 247{ 248 if (!tickEvent.scheduled()) |
249 schedule(tickEvent, clockEdge(1)); | 249 schedule(tickEvent, clockEdge(Cycles(1))); |
250 251 if (++noResponseCycles >= 500000) { 252 if (issueDmas) { 253 cerr << "DMA tester "; 254 } 255 cerr << name() << ": deadlocked at cycle " << curTick() << endl; 256 fatal(""); 257 } --- 143 unchanged lines hidden --- | 250 251 if (++noResponseCycles >= 500000) { 252 if (issueDmas) { 253 cerr << "DMA tester "; 254 } 255 cerr << name() << ": deadlocked at cycle " << curTick() << endl; 256 fatal(""); 257 } --- 143 unchanged lines hidden --- |