memtest.cc (7804:42f343470ee3) memtest.cc (7823:dac01f14f20f)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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64}
65
66Tick
67MemTest::CpuPort::recvAtomic(PacketPtr pkt)
68{
69 // must be snoop upcall
70 assert(pkt->isRequest());
71 assert(pkt->getDest() == Packet::Broadcast);
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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64}
65
66Tick
67MemTest::CpuPort::recvAtomic(PacketPtr pkt)
68{
69 // must be snoop upcall
70 assert(pkt->isRequest());
71 assert(pkt->getDest() == Packet::Broadcast);
72 return curTick;
72 return curTick();
73}
74
75void
76MemTest::CpuPort::recvFunctional(PacketPtr pkt)
77{
78 //Do nothing if we see one come through
73}
74
75void
76MemTest::CpuPort::recvFunctional(PacketPtr pkt)
77{
78 //Do nothing if we see one come through
79// if (curTick != 0)//Supress warning durring initialization
79// if (curTick() != 0)//Supress warning durring initialization
80// warn("Functional Writes not implemented in MemTester\n");
81 //Need to find any response values that intersect and update
82 return;
83}
84
85void
86MemTest::CpuPort::recvStatusChange(Status status)
87{

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215 outstandingAddrs.find(req->getPaddr());
216 assert(removeAddr != outstandingAddrs.end());
217 outstandingAddrs.erase(removeAddr);
218
219 if (pkt->isRead()) {
220 if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
221 panic("%s: read of %x (blk %x) @ cycle %d "
222 "returns %x, expected %x\n", name(),
80// warn("Functional Writes not implemented in MemTester\n");
81 //Need to find any response values that intersect and update
82 return;
83}
84
85void
86MemTest::CpuPort::recvStatusChange(Status status)
87{

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215 outstandingAddrs.find(req->getPaddr());
216 assert(removeAddr != outstandingAddrs.end());
217 outstandingAddrs.erase(removeAddr);
218
219 if (pkt->isRead()) {
220 if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
221 panic("%s: read of %x (blk %x) @ cycle %d "
222 "returns %x, expected %x\n", name(),
223 req->getPaddr(), blockAddr(req->getPaddr()), curTick,
223 req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
224 *pkt_data, *data);
225 }
226
227 numReads++;
228 numReadsStat++;
229
230 if (numReads == (uint64_t)nextProgressMessage) {
231 ccprintf(cerr, "%s: completed %d read accesses @%d\n",
224 *pkt_data, *data);
225 }
226
227 numReads++;
228 numReadsStat++;
229
230 if (numReads == (uint64_t)nextProgressMessage) {
231 ccprintf(cerr, "%s: completed %d read accesses @%d\n",
232 name(), numReads, curTick);
232 name(), numReads, curTick());
233 nextProgressMessage += progressInterval;
234 }
235
236 if (maxLoads != 0 && numReads >= maxLoads)
237 exitSimLoop("maximum number of loads reached");
238 } else {
239 assert(pkt->isWrite());
240 numWritesStat++;

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267 .desc("number of copy accesses completed")
268 ;
269}
270
271void
272MemTest::tick()
273{
274 if (!tickEvent.scheduled())
233 nextProgressMessage += progressInterval;
234 }
235
236 if (maxLoads != 0 && numReads >= maxLoads)
237 exitSimLoop("maximum number of loads reached");
238 } else {
239 assert(pkt->isWrite());
240 numWritesStat++;

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267 .desc("number of copy accesses completed")
268 ;
269}
270
271void
272MemTest::tick()
273{
274 if (!tickEvent.scheduled())
275 schedule(tickEvent, curTick + ticks(1));
275 schedule(tickEvent, curTick() + ticks(1));
276
277 if (++noResponseCycles >= 500000) {
278 if (issueDmas) {
279 cerr << "DMA tester ";
280 }
276
277 if (++noResponseCycles >= 500000) {
278 if (issueDmas) {
279 cerr << "DMA tester ";
280 }
281 cerr << name() << ": deadlocked at cycle " << curTick << endl;
281 cerr << name() << ": deadlocked at cycle " << curTick() << endl;
282 fatal("");
283 }
284
285 if (accessRetry || (issueDmas && dmaOutstanding)) {
286 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
287 return;
288 }
289

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283 }
284
285 if (accessRetry || (issueDmas && dmaOutstanding)) {
286 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
287 return;
288 }
289

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