1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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48#include "sim/stats.hh"
49#include "sim/system.hh"
50
51using namespace std;
52
53int TESTER_ALLOCATOR=0;
54
55bool
56MemTest::CpuPort::recvTiming(PacketPtr pkt)
56MemTest::CpuPort::recvTimingResp(PacketPtr pkt)
57{
58 assert(pkt->isResponse());
58 memtest->completeRequest(pkt);
59 return true;
60}
61
62void
63MemTest::CpuPort::recvRetry()
64{
65 memtest->doRetry();
66}
67
68void
69MemTest::sendPkt(PacketPtr pkt) {
70 if (atomic) {
71 cachePort.sendAtomic(pkt);
72 completeRequest(pkt);
73 }
75 else if (!cachePort.sendTiming(pkt)) {
74 else if (!cachePort.sendTimingReq(pkt)) {
75 DPRINTF(MemTest, "accessRetry setting to true\n");
76
77 //
78 // dma requests should never be retried
79 //
80 if (issueDmas) {
81 panic("Nacked DMA requests are not supported\n");
82 }

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373 sendPkt(pkt);
374 }
375 }
376}
377
378void
379MemTest::doRetry()
380{
382 if (cachePort.sendTiming(retryPkt)) {
381 if (cachePort.sendTimingReq(retryPkt)) {
382 DPRINTF(MemTest, "accessRetry setting to false\n");
383 accessRetry = false;
384 retryPkt = NULL;
385 }
386}
387
388
389void
390MemTest::printAddr(Addr a)
391{
392 cachePort.printAddr(a);
393}
394
395
396MemTest *
397MemTestParams::create()
398{
399 return new MemTest(this);
400}