1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "debug/MemTest.hh"
43#include "mem/mem_object.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/sim_events.hh"
48#include "sim/stats.hh"
49#include "sim/system.hh"
50
51using namespace std;
52
53int TESTER_ALLOCATOR=0;
54
55bool
56MemTest::CpuPort::recvTiming(PacketPtr pkt)
57{
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "debug/MemTest.hh"
43#include "mem/mem_object.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/sim_events.hh"
48#include "sim/stats.hh"
49#include "sim/system.hh"
50
51using namespace std;
52
53int TESTER_ALLOCATOR=0;
54
55bool
56MemTest::CpuPort::recvTiming(PacketPtr pkt)
57{
|
88MemTest::CpuPort::recvRetry()
89{
90 memtest->doRetry();
91}
92
93void
94MemTest::sendPkt(PacketPtr pkt) {
95 if (atomic) {
96 cachePort.sendAtomic(pkt);
97 completeRequest(pkt);
98 }
99 else if (!cachePort.sendTiming(pkt)) {
100 DPRINTF(MemTest, "accessRetry setting to true\n");
101
102 //
103 // dma requests should never be retried
104 //
105 if (issueDmas) {
106 panic("Nacked DMA requests are not supported\n");
107 }
108 accessRetry = true;
109 retryPkt = pkt;
110 } else {
111 if (issueDmas) {
112 dmaOutstanding = true;
113 }
114 }
115
116}
117
118MemTest::MemTest(const Params *p)
119 : MemObject(p),
120 tickEvent(this),
121 cachePort("test", this),
122 funcPort("functional", this),
123 funcProxy(funcPort),
124 retryPkt(NULL),
125// mainMem(main_mem),
126// checkMem(check_mem),
127 size(p->memory_size),
128 percentReads(p->percent_reads),
129 percentFunctional(p->percent_functional),
130 percentUncacheable(p->percent_uncacheable),
131 issueDmas(p->issue_dmas),
132 masterId(p->sys->getMasterId(name())),
133 progressInterval(p->progress_interval),
134 nextProgressMessage(p->progress_interval),
135 percentSourceUnaligned(p->percent_source_unaligned),
136 percentDestUnaligned(p->percent_dest_unaligned),
137 maxLoads(p->max_loads),
138 atomic(p->atomic),
139 suppress_func_warnings(p->suppress_func_warnings)
140{
141 id = TESTER_ALLOCATOR++;
142
143 // Needs to be masked off once we know the block size.
144 traceBlockAddr = p->trace_addr;
145 baseAddr1 = 0x100000;
146 baseAddr2 = 0x400000;
147 uncacheAddr = 0x800000;
148
149 // set up counters
150 noResponseCycles = 0;
151 numReads = 0;
152 numWrites = 0;
153 schedule(tickEvent, 0);
154
155 accessRetry = false;
156 dmaOutstanding = false;
157}
158
159MasterPort &
160MemTest::getMasterPort(const std::string &if_name, int idx)
161{
162 if (if_name == "functional")
163 return funcPort;
164 else if (if_name == "test")
165 return cachePort;
166 else
167 return MemObject::getMasterPort(if_name, idx);
168}
169
170void
171MemTest::init()
172{
173 // By the time init() is called, the ports should be hooked up.
174 blockSize = cachePort.peerBlockSize();
175 blockAddrMask = blockSize - 1;
176 traceBlockAddr = blockAddr(traceBlockAddr);
177
178 // initial memory contents for both physical memory and functional
179 // memory should be 0; no need to initialize them.
180}
181
182
183void
184MemTest::completeRequest(PacketPtr pkt)
185{
186 Request *req = pkt->req;
187
188 if (issueDmas) {
189 dmaOutstanding = false;
190 }
191
192 DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n",
193 pkt->isWrite() ? "write" : "read",
194 req->getPaddr(), blockAddr(req->getPaddr()),
195 pkt->isError() ? "error" : "success");
196
197 MemTestSenderState *state =
198 dynamic_cast<MemTestSenderState *>(pkt->senderState);
199
200 uint8_t *data = state->data;
201 uint8_t *pkt_data = pkt->getPtr<uint8_t>();
202
203 //Remove the address from the list of outstanding
204 std::set<unsigned>::iterator removeAddr =
205 outstandingAddrs.find(req->getPaddr());
206 assert(removeAddr != outstandingAddrs.end());
207 outstandingAddrs.erase(removeAddr);
208
209 if (pkt->isError()) {
210 if (!suppress_func_warnings) {
211 warn("Functional Access failed for %x at %x\n",
212 pkt->isWrite() ? "write" : "read", req->getPaddr());
213 }
214 } else {
215 if (pkt->isRead()) {
216 if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
217 panic("%s: read of %x (blk %x) @ cycle %d "
218 "returns %x, expected %x\n", name(),
219 req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
220 *pkt_data, *data);
221 }
222
223 numReads++;
224 numReadsStat++;
225
226 if (numReads == (uint64_t)nextProgressMessage) {
227 ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n",
228 name(), numReads, numWrites, curTick());
229 nextProgressMessage += progressInterval;
230 }
231
232 if (maxLoads != 0 && numReads >= maxLoads)
233 exitSimLoop("maximum number of loads reached");
234 } else {
235 assert(pkt->isWrite());
236 funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
237 numWrites++;
238 numWritesStat++;
239 }
240 }
241
242 noResponseCycles = 0;
243 delete state;
244 delete [] data;
245 delete pkt->req;
246 delete pkt;
247}
248
249void
250MemTest::regStats()
251{
252 using namespace Stats;
253
254 numReadsStat
255 .name(name() + ".num_reads")
256 .desc("number of read accesses completed")
257 ;
258
259 numWritesStat
260 .name(name() + ".num_writes")
261 .desc("number of write accesses completed")
262 ;
263
264 numCopiesStat
265 .name(name() + ".num_copies")
266 .desc("number of copy accesses completed")
267 ;
268}
269
270void
271MemTest::tick()
272{
273 if (!tickEvent.scheduled())
274 schedule(tickEvent, curTick() + ticks(1));
275
276 if (++noResponseCycles >= 500000) {
277 if (issueDmas) {
278 cerr << "DMA tester ";
279 }
280 cerr << name() << ": deadlocked at cycle " << curTick() << endl;
281 fatal("");
282 }
283
284 if (accessRetry || (issueDmas && dmaOutstanding)) {
285 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
286 return;
287 }
288
289 //make new request
290 unsigned cmd = random() % 100;
291 unsigned offset = random() % size;
292 unsigned base = random() % 2;
293 uint64_t data = random();
294 unsigned access_size = random() % 4;
295 bool uncacheable = (random() % 100) < percentUncacheable;
296
297 unsigned dma_access_size = random() % 4;
298
299 //If we aren't doing copies, use id as offset, and do a false sharing
300 //mem tester
301 //We can eliminate the lower bits of the offset, and then use the id
302 //to offset within the blks
303 offset = blockAddr(offset);
304 offset += id;
305 access_size = 0;
306 dma_access_size = 0;
307
308 Request *req = new Request();
309 Request::Flags flags;
310 Addr paddr;
311
312 if (uncacheable) {
313 flags.set(Request::UNCACHEABLE);
314 paddr = uncacheAddr + offset;
315 } else {
316 paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
317 }
318 bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
319
320 if (issueDmas) {
321 paddr &= ~((1 << dma_access_size) - 1);
322 req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
323 req->setThreadContext(id,0);
324 } else {
325 paddr &= ~((1 << access_size) - 1);
326 req->setPhys(paddr, 1 << access_size, flags, masterId);
327 req->setThreadContext(id,0);
328 }
329 assert(req->getSize() == 1);
330
331 uint8_t *result = new uint8_t[8];
332
333 if (cmd < percentReads) {
334 // read
335
336 // For now we only allow one outstanding request per address
337 // per tester This means we assume CPU does write forwarding
338 // to reads that alias something in the cpu store buffer.
339 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
340 delete [] result;
341 delete req;
342 return;
343 }
344
345 outstandingAddrs.insert(paddr);
346
347 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
348 funcProxy.readBlob(req->getPaddr(), result, req->getSize());
349
350 DPRINTF(MemTest,
351 "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
352 id, do_functional ? "functional " : "", req->getPaddr(),
353 blockAddr(req->getPaddr()), *result);
354
355 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
356 pkt->setSrc(0);
357 pkt->dataDynamicArray(new uint8_t[req->getSize()]);
358 MemTestSenderState *state = new MemTestSenderState(result);
359 pkt->senderState = state;
360
361 if (do_functional) {
362 assert(pkt->needsResponse());
363 pkt->setSuppressFuncError();
364 cachePort.sendFunctional(pkt);
365 completeRequest(pkt);
366 } else {
367 sendPkt(pkt);
368 }
369 } else {
370 // write
371
372 // For now we only allow one outstanding request per addreess
373 // per tester. This means we assume CPU does write forwarding
374 // to reads that alias something in the cpu store buffer.
375 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
376 delete [] result;
377 delete req;
378 return;
379 }
380
381 outstandingAddrs.insert(paddr);
382
383 DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
384 do_functional ? "functional " : "", req->getPaddr(),
385 blockAddr(req->getPaddr()), data & 0xff);
386
387 PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
388 pkt->setSrc(0);
389 uint8_t *pkt_data = new uint8_t[req->getSize()];
390 pkt->dataDynamicArray(pkt_data);
391 memcpy(pkt_data, &data, req->getSize());
392 MemTestSenderState *state = new MemTestSenderState(result);
393 pkt->senderState = state;
394
395 if (do_functional) {
396 pkt->setSuppressFuncError();
397 cachePort.sendFunctional(pkt);
398 completeRequest(pkt);
399 } else {
400 sendPkt(pkt);
401 }
402 }
403}
404
405void
406MemTest::doRetry()
407{
408 if (cachePort.sendTiming(retryPkt)) {
409 DPRINTF(MemTest, "accessRetry setting to false\n");
410 accessRetry = false;
411 retryPkt = NULL;
412 }
413}
414
415
416void
417MemTest::printAddr(Addr a)
418{
419 cachePort.printAddr(a);
420}
421
422
423MemTest *
424MemTestParams::create()
425{
426 return new MemTest(this);
427}
| 64MemTest::CpuPort::recvRetry()
65{
66 memtest->doRetry();
67}
68
69void
70MemTest::sendPkt(PacketPtr pkt) {
71 if (atomic) {
72 cachePort.sendAtomic(pkt);
73 completeRequest(pkt);
74 }
75 else if (!cachePort.sendTiming(pkt)) {
76 DPRINTF(MemTest, "accessRetry setting to true\n");
77
78 //
79 // dma requests should never be retried
80 //
81 if (issueDmas) {
82 panic("Nacked DMA requests are not supported\n");
83 }
84 accessRetry = true;
85 retryPkt = pkt;
86 } else {
87 if (issueDmas) {
88 dmaOutstanding = true;
89 }
90 }
91
92}
93
94MemTest::MemTest(const Params *p)
95 : MemObject(p),
96 tickEvent(this),
97 cachePort("test", this),
98 funcPort("functional", this),
99 funcProxy(funcPort),
100 retryPkt(NULL),
101// mainMem(main_mem),
102// checkMem(check_mem),
103 size(p->memory_size),
104 percentReads(p->percent_reads),
105 percentFunctional(p->percent_functional),
106 percentUncacheable(p->percent_uncacheable),
107 issueDmas(p->issue_dmas),
108 masterId(p->sys->getMasterId(name())),
109 progressInterval(p->progress_interval),
110 nextProgressMessage(p->progress_interval),
111 percentSourceUnaligned(p->percent_source_unaligned),
112 percentDestUnaligned(p->percent_dest_unaligned),
113 maxLoads(p->max_loads),
114 atomic(p->atomic),
115 suppress_func_warnings(p->suppress_func_warnings)
116{
117 id = TESTER_ALLOCATOR++;
118
119 // Needs to be masked off once we know the block size.
120 traceBlockAddr = p->trace_addr;
121 baseAddr1 = 0x100000;
122 baseAddr2 = 0x400000;
123 uncacheAddr = 0x800000;
124
125 // set up counters
126 noResponseCycles = 0;
127 numReads = 0;
128 numWrites = 0;
129 schedule(tickEvent, 0);
130
131 accessRetry = false;
132 dmaOutstanding = false;
133}
134
135MasterPort &
136MemTest::getMasterPort(const std::string &if_name, int idx)
137{
138 if (if_name == "functional")
139 return funcPort;
140 else if (if_name == "test")
141 return cachePort;
142 else
143 return MemObject::getMasterPort(if_name, idx);
144}
145
146void
147MemTest::init()
148{
149 // By the time init() is called, the ports should be hooked up.
150 blockSize = cachePort.peerBlockSize();
151 blockAddrMask = blockSize - 1;
152 traceBlockAddr = blockAddr(traceBlockAddr);
153
154 // initial memory contents for both physical memory and functional
155 // memory should be 0; no need to initialize them.
156}
157
158
159void
160MemTest::completeRequest(PacketPtr pkt)
161{
162 Request *req = pkt->req;
163
164 if (issueDmas) {
165 dmaOutstanding = false;
166 }
167
168 DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n",
169 pkt->isWrite() ? "write" : "read",
170 req->getPaddr(), blockAddr(req->getPaddr()),
171 pkt->isError() ? "error" : "success");
172
173 MemTestSenderState *state =
174 dynamic_cast<MemTestSenderState *>(pkt->senderState);
175
176 uint8_t *data = state->data;
177 uint8_t *pkt_data = pkt->getPtr<uint8_t>();
178
179 //Remove the address from the list of outstanding
180 std::set<unsigned>::iterator removeAddr =
181 outstandingAddrs.find(req->getPaddr());
182 assert(removeAddr != outstandingAddrs.end());
183 outstandingAddrs.erase(removeAddr);
184
185 if (pkt->isError()) {
186 if (!suppress_func_warnings) {
187 warn("Functional Access failed for %x at %x\n",
188 pkt->isWrite() ? "write" : "read", req->getPaddr());
189 }
190 } else {
191 if (pkt->isRead()) {
192 if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
193 panic("%s: read of %x (blk %x) @ cycle %d "
194 "returns %x, expected %x\n", name(),
195 req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
196 *pkt_data, *data);
197 }
198
199 numReads++;
200 numReadsStat++;
201
202 if (numReads == (uint64_t)nextProgressMessage) {
203 ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n",
204 name(), numReads, numWrites, curTick());
205 nextProgressMessage += progressInterval;
206 }
207
208 if (maxLoads != 0 && numReads >= maxLoads)
209 exitSimLoop("maximum number of loads reached");
210 } else {
211 assert(pkt->isWrite());
212 funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
213 numWrites++;
214 numWritesStat++;
215 }
216 }
217
218 noResponseCycles = 0;
219 delete state;
220 delete [] data;
221 delete pkt->req;
222 delete pkt;
223}
224
225void
226MemTest::regStats()
227{
228 using namespace Stats;
229
230 numReadsStat
231 .name(name() + ".num_reads")
232 .desc("number of read accesses completed")
233 ;
234
235 numWritesStat
236 .name(name() + ".num_writes")
237 .desc("number of write accesses completed")
238 ;
239
240 numCopiesStat
241 .name(name() + ".num_copies")
242 .desc("number of copy accesses completed")
243 ;
244}
245
246void
247MemTest::tick()
248{
249 if (!tickEvent.scheduled())
250 schedule(tickEvent, curTick() + ticks(1));
251
252 if (++noResponseCycles >= 500000) {
253 if (issueDmas) {
254 cerr << "DMA tester ";
255 }
256 cerr << name() << ": deadlocked at cycle " << curTick() << endl;
257 fatal("");
258 }
259
260 if (accessRetry || (issueDmas && dmaOutstanding)) {
261 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
262 return;
263 }
264
265 //make new request
266 unsigned cmd = random() % 100;
267 unsigned offset = random() % size;
268 unsigned base = random() % 2;
269 uint64_t data = random();
270 unsigned access_size = random() % 4;
271 bool uncacheable = (random() % 100) < percentUncacheable;
272
273 unsigned dma_access_size = random() % 4;
274
275 //If we aren't doing copies, use id as offset, and do a false sharing
276 //mem tester
277 //We can eliminate the lower bits of the offset, and then use the id
278 //to offset within the blks
279 offset = blockAddr(offset);
280 offset += id;
281 access_size = 0;
282 dma_access_size = 0;
283
284 Request *req = new Request();
285 Request::Flags flags;
286 Addr paddr;
287
288 if (uncacheable) {
289 flags.set(Request::UNCACHEABLE);
290 paddr = uncacheAddr + offset;
291 } else {
292 paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
293 }
294 bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
295
296 if (issueDmas) {
297 paddr &= ~((1 << dma_access_size) - 1);
298 req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
299 req->setThreadContext(id,0);
300 } else {
301 paddr &= ~((1 << access_size) - 1);
302 req->setPhys(paddr, 1 << access_size, flags, masterId);
303 req->setThreadContext(id,0);
304 }
305 assert(req->getSize() == 1);
306
307 uint8_t *result = new uint8_t[8];
308
309 if (cmd < percentReads) {
310 // read
311
312 // For now we only allow one outstanding request per address
313 // per tester This means we assume CPU does write forwarding
314 // to reads that alias something in the cpu store buffer.
315 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
316 delete [] result;
317 delete req;
318 return;
319 }
320
321 outstandingAddrs.insert(paddr);
322
323 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
324 funcProxy.readBlob(req->getPaddr(), result, req->getSize());
325
326 DPRINTF(MemTest,
327 "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
328 id, do_functional ? "functional " : "", req->getPaddr(),
329 blockAddr(req->getPaddr()), *result);
330
331 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
332 pkt->setSrc(0);
333 pkt->dataDynamicArray(new uint8_t[req->getSize()]);
334 MemTestSenderState *state = new MemTestSenderState(result);
335 pkt->senderState = state;
336
337 if (do_functional) {
338 assert(pkt->needsResponse());
339 pkt->setSuppressFuncError();
340 cachePort.sendFunctional(pkt);
341 completeRequest(pkt);
342 } else {
343 sendPkt(pkt);
344 }
345 } else {
346 // write
347
348 // For now we only allow one outstanding request per addreess
349 // per tester. This means we assume CPU does write forwarding
350 // to reads that alias something in the cpu store buffer.
351 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
352 delete [] result;
353 delete req;
354 return;
355 }
356
357 outstandingAddrs.insert(paddr);
358
359 DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
360 do_functional ? "functional " : "", req->getPaddr(),
361 blockAddr(req->getPaddr()), data & 0xff);
362
363 PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
364 pkt->setSrc(0);
365 uint8_t *pkt_data = new uint8_t[req->getSize()];
366 pkt->dataDynamicArray(pkt_data);
367 memcpy(pkt_data, &data, req->getSize());
368 MemTestSenderState *state = new MemTestSenderState(result);
369 pkt->senderState = state;
370
371 if (do_functional) {
372 pkt->setSuppressFuncError();
373 cachePort.sendFunctional(pkt);
374 completeRequest(pkt);
375 } else {
376 sendPkt(pkt);
377 }
378 }
379}
380
381void
382MemTest::doRetry()
383{
384 if (cachePort.sendTiming(retryPkt)) {
385 DPRINTF(MemTest, "accessRetry setting to false\n");
386 accessRetry = false;
387 retryPkt = NULL;
388 }
389}
390
391
392void
393MemTest::printAddr(Addr a)
394{
395 cachePort.printAddr(a);
396}
397
398
399MemTest *
400MemTestParams::create()
401{
402 return new MemTest(this);
403}
|