1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 39 unchanged lines hidden (view full) ---

48#include "sim/stats.hh"
49#include "sim/system.hh"
50
51using namespace std;
52
53int TESTER_ALLOCATOR=0;
54
55bool
56MemTest::CpuPort::recvTiming(PacketPtr pkt)
57{
58 assert(pkt->isResponse());
59 memtest->completeRequest(pkt);
60 return true;
61}
62
63void
64MemTest::CpuPort::recvRetry()
65{
66 memtest->doRetry();
67}
68
69void
70MemTest::sendPkt(PacketPtr pkt) {
71 if (atomic) {
72 cachePort.sendAtomic(pkt);
73 completeRequest(pkt);
74 }
75 else if (!cachePort.sendTiming(pkt)) {
76 DPRINTF(MemTest, "accessRetry setting to true\n");
77
78 //
79 // dma requests should never be retried
80 //
81 if (issueDmas) {
82 panic("Nacked DMA requests are not supported\n");
83 }

--- 290 unchanged lines hidden (view full) ---

374 sendPkt(pkt);
375 }
376 }
377}
378
379void
380MemTest::doRetry()
381{
382 if (cachePort.sendTiming(retryPkt)) {
383 DPRINTF(MemTest, "accessRetry setting to false\n");
384 accessRetry = false;
385 retryPkt = NULL;
386 }
387}
388
389
390void
391MemTest::printAddr(Addr a)
392{
393 cachePort.printAddr(a);
394}
395
396
397MemTest *
398MemTestParams::create()
399{
400 return new MemTest(this);
401}