1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 34 unchanged lines hidden (view full) ---

43 */
44
45#include "cpu/testers/memtest/memtest.hh"
46
47#include "base/random.hh"
48#include "base/statistics.hh"
49#include "base/trace.hh"
50#include "debug/MemTest.hh"
51#include "mem/mem_object.hh"
52#include "sim/sim_exit.hh"
53#include "sim/stats.hh"
54#include "sim/system.hh"
55
56using namespace std;
57
58unsigned int TESTER_ALLOCATOR = 0;
59

--- 20 unchanged lines hidden (view full) ---

80 retryPkt = pkt;
81 return false;
82 }
83 }
84 return true;
85}
86
87MemTest::MemTest(const Params *p)
88 : MemObject(p),
89 tickEvent([this]{ tick(); }, name()),
90 noRequestEvent([this]{ noRequest(); }, name()),
91 noResponseEvent([this]{ noResponse(); }, name()),
92 port("port", *this),
93 retryPkt(nullptr),
94 size(p->size),
95 interval(p->interval),
96 percentReads(p->percent_reads),

--- 28 unchanged lines hidden (view full) ---

125}
126
127Port &
128MemTest::getPort(const std::string &if_name, PortID idx)
129{
130 if (if_name == "port")
131 return port;
132 else
133 return MemObject::getPort(if_name, idx);
134}
135
136void
137MemTest::completeRequest(PacketPtr pkt, bool functional)
138{
139 const RequestPtr &req = pkt->req;
140 assert(req->getSize() == 1);
141

--- 50 unchanged lines hidden (view full) ---

192
193 // finally shift the response timeout forward
194 reschedule(noResponseEvent, clockEdge(progressCheck), true);
195}
196
197void
198MemTest::regStats()
199{
200 MemObject::regStats();
201
202 using namespace Stats;
203
204 numReadsStat
205 .name(name() + ".num_reads")
206 .desc("number of read accesses completed")
207 ;
208

--- 130 unchanged lines hidden ---