SeriesRequestGenerator.cc (9365:644be05ee7c2) SeriesRequestGenerator.cc (10348:c91b23c72d5e)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 13 unchanged lines hidden (view full) ---

22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "base/random.hh"
30#include "cpu/testers/directedtest/DirectedGenerator.hh"
31#include "cpu/testers/directedtest/RubyDirectedTester.hh"
32#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
33#include "debug/DirectedTest.hh"
34
35SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
36 : DirectedGenerator(p),
37 m_addr_increment_size(p->addr_increment_size),

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55 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
56
57 Request::Flags flags;
58
59 // For simplicity, requests are assumed to be 1 byte-sized
60 Request *req = new Request(m_address, 1, flags, masterId);
61
62 Packet::Command cmd;
31#include "cpu/testers/directedtest/DirectedGenerator.hh"
32#include "cpu/testers/directedtest/RubyDirectedTester.hh"
33#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
34#include "debug/DirectedTest.hh"
35
36SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
37 : DirectedGenerator(p),
38 m_addr_increment_size(p->addr_increment_size),

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56 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
57
58 Request::Flags flags;
59
60 // For simplicity, requests are assumed to be 1 byte-sized
61 Request *req = new Request(m_address, 1, flags, masterId);
62
63 Packet::Command cmd;
63 bool do_write = ((random() % 100) < m_percent_writes);
64 bool do_write = (random_mt.random(0, 100) < m_percent_writes);
64 if (do_write) {
65 cmd = MemCmd::WriteReq;
66 } else {
67 cmd = MemCmd::ReadReq;
68 }
69
70 PacketPtr pkt = new Packet(req, cmd);
71 uint8_t* dummyData = new uint8_t;

--- 44 unchanged lines hidden --- 		65 if (do_write) {
66 cmd = MemCmd::WriteReq;
67 } else {
68 cmd = MemCmd::ReadReq;
69 }
70
71 PacketPtr pkt = new Packet(req, cmd);
72 uint8_t* dummyData = new uint8_t;

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