SeriesRequestGenerator.cc (8975:7f36d4436074) SeriesRequestGenerator.cc (9365:644be05ee7c2)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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28 */
29
30#include "cpu/testers/directedtest/DirectedGenerator.hh"
31#include "cpu/testers/directedtest/RubyDirectedTester.hh"
32#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
33#include "debug/DirectedTest.hh"
34
35SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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28 */
29
30#include "cpu/testers/directedtest/DirectedGenerator.hh"
31#include "cpu/testers/directedtest/RubyDirectedTester.hh"
32#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
33#include "debug/DirectedTest.hh"
34
35SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
36 : DirectedGenerator(p)
36 : DirectedGenerator(p),
37 m_addr_increment_size(p->addr_increment_size),
38 m_percent_writes(p->percent_writes)
37{
38 m_status = SeriesRequestGeneratorStatus_Thinking;
39 m_active_node = 0;
40 m_address = 0x0;
39{
40 m_status = SeriesRequestGeneratorStatus_Thinking;
41 m_active_node = 0;
42 m_address = 0x0;
41 m_addr_increment_size = p->addr_increment_size;
42 m_issue_writes = p->issue_writes;
43}
44
45SeriesRequestGenerator::~SeriesRequestGenerator()
46{
47}
48
49bool
50SeriesRequestGenerator::initiate()

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55 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
56
57 Request::Flags flags;
58
59 // For simplicity, requests are assumed to be 1 byte-sized
60 Request *req = new Request(m_address, 1, flags, masterId);
61
62 Packet::Command cmd;
43}
44
45SeriesRequestGenerator::~SeriesRequestGenerator()
46{
47}
48
49bool
50SeriesRequestGenerator::initiate()

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55 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
56
57 Request::Flags flags;
58
59 // For simplicity, requests are assumed to be 1 byte-sized
60 Request *req = new Request(m_address, 1, flags, masterId);
61
62 Packet::Command cmd;
63 if (m_issue_writes) {
63 bool do_write = ((random() % 100) < m_percent_writes);
64 if (do_write) {
64 cmd = MemCmd::WriteReq;
65 } else {
66 cmd = MemCmd::ReadReq;
67 }
65 cmd = MemCmd::WriteReq;
66 } else {
67 cmd = MemCmd::ReadReq;
68 }
69
68 PacketPtr pkt = new Packet(req, cmd);
69 uint8_t* dummyData = new uint8_t;
70 *dummyData = 0;
71 pkt->dataDynamic(dummyData);
72
73 if (port->sendTimingReq(pkt)) {
74 DPRINTF(DirectedTest, "initiating request - successful\n");
75 m_status = SeriesRequestGeneratorStatus_Request_Pending;

--- 38 unchanged lines hidden --- 		70 PacketPtr pkt = new Packet(req, cmd);
71 uint8_t* dummyData = new uint8_t;
72 *dummyData = 0;
73 pkt->dataDynamic(dummyData);
74
75 if (port->sendTimingReq(pkt)) {
76 DPRINTF(DirectedTest, "initiating request - successful\n");
77 m_status = SeriesRequestGeneratorStatus_Request_Pending;

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