1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "base/random.hh"
31#include "cpu/testers/directedtest/DirectedGenerator.hh"
32#include "cpu/testers/directedtest/RubyDirectedTester.hh"
33#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
34#include "debug/DirectedTest.hh"
35
36SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
37 : DirectedGenerator(p),
38 m_addr_increment_size(p->addr_increment_size),
39 m_percent_writes(p->percent_writes)
40{
41 m_status = SeriesRequestGeneratorStatus_Thinking;
42 m_active_node = 0;
43 m_address = 0x0;
44}
45
46SeriesRequestGenerator::~SeriesRequestGenerator()
47{
48}
49
50bool
51SeriesRequestGenerator::initiate()
52{
53 DPRINTF(DirectedTest, "initiating request\n");
54 assert(m_status == SeriesRequestGeneratorStatus_Thinking);
55
56 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
57
58 Request::Flags flags;
59
60 // For simplicity, requests are assumed to be 1 byte-sized
61 Request *req = new Request(m_address, 1, flags, masterId);
62
63 Packet::Command cmd;
64 bool do_write = (random_mt.random(0, 100) < m_percent_writes);
65 if (do_write) {
66 cmd = MemCmd::WriteReq;
67 } else {
68 cmd = MemCmd::ReadReq;
69 }
70
71 PacketPtr pkt = new Packet(req, cmd);
72 pkt->allocate();
73
74 if (port->sendTimingReq(pkt)) {
75 DPRINTF(DirectedTest, "initiating request - successful\n");
76 m_status = SeriesRequestGeneratorStatus_Request_Pending;
77 return true;
78 } else {
79 // If the packet did not issue, must delete
80 // Note: No need to delete the data, the packet destructor
81 // will delete it
82 delete pkt->req;
83 delete pkt;
84
85 DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
86 return false;
87 }
88}
89
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