1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "cpu/testers/directedtest/DirectedGenerator.hh"
31#include "cpu/testers/directedtest/RubyDirectedTester.hh"
32#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
33#include "debug/DirectedTest.hh"
34
35SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
| 1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "cpu/testers/directedtest/DirectedGenerator.hh"
31#include "cpu/testers/directedtest/RubyDirectedTester.hh"
32#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
33#include "debug/DirectedTest.hh"
34
35SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
|
36 : DirectedGenerator(p)
| 36 : DirectedGenerator(p),
37 m_addr_increment_size(p->addr_increment_size),
38 m_percent_writes(p->percent_writes)
|
37{
38 m_status = SeriesRequestGeneratorStatus_Thinking;
39 m_active_node = 0;
40 m_address = 0x0;
| 39{
40 m_status = SeriesRequestGeneratorStatus_Thinking;
41 m_active_node = 0;
42 m_address = 0x0;
|
41 m_addr_increment_size = p->addr_increment_size;
42 m_issue_writes = p->issue_writes;
| |
43}
44
45SeriesRequestGenerator::~SeriesRequestGenerator()
46{
47}
48
49bool
50SeriesRequestGenerator::initiate()
51{
52 DPRINTF(DirectedTest, "initiating request\n");
53 assert(m_status == SeriesRequestGeneratorStatus_Thinking);
54
55 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
56
57 Request::Flags flags;
58
59 // For simplicity, requests are assumed to be 1 byte-sized
60 Request *req = new Request(m_address, 1, flags, masterId);
61
62 Packet::Command cmd;
| 43}
44
45SeriesRequestGenerator::~SeriesRequestGenerator()
46{
47}
48
49bool
50SeriesRequestGenerator::initiate()
51{
52 DPRINTF(DirectedTest, "initiating request\n");
53 assert(m_status == SeriesRequestGeneratorStatus_Thinking);
54
55 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
56
57 Request::Flags flags;
58
59 // For simplicity, requests are assumed to be 1 byte-sized
60 Request *req = new Request(m_address, 1, flags, masterId);
61
62 Packet::Command cmd;
|
63 if (m_issue_writes) {
| 63 bool do_write = ((random() % 100) < m_percent_writes);
64 if (do_write) {
|
64 cmd = MemCmd::WriteReq;
65 } else {
66 cmd = MemCmd::ReadReq;
67 }
| 65 cmd = MemCmd::WriteReq;
66 } else {
67 cmd = MemCmd::ReadReq;
68 }
|
| 69
|
68 PacketPtr pkt = new Packet(req, cmd);
69 uint8_t* dummyData = new uint8_t;
70 *dummyData = 0;
71 pkt->dataDynamic(dummyData);
72
73 if (port->sendTimingReq(pkt)) {
74 DPRINTF(DirectedTest, "initiating request - successful\n");
75 m_status = SeriesRequestGeneratorStatus_Request_Pending;
76 return true;
77 } else {
78 // If the packet did not issue, must delete
79 // Note: No need to delete the data, the packet destructor
80 // will delete it
81 delete pkt->req;
82 delete pkt;
83
84 DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
85 return false;
86 }
87}
88
89void
90SeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
91{
92 assert(m_active_node == proc);
93 assert(m_address == address);
94 assert(m_status == SeriesRequestGeneratorStatus_Request_Pending);
95
96 m_status = SeriesRequestGeneratorStatus_Thinking;
97 m_active_node++;
98 if (m_active_node == m_num_cpus) {
99 //
100 // Cycle of requests completed, increment cycle completions and restart
101 // at cpu zero
102 //
103 m_directed_tester->incrementCycleCompletions();
104 m_address += m_addr_increment_size;
105 m_active_node = 0;
106 }
107}
108
109SeriesRequestGenerator *
110SeriesRequestGeneratorParams::create()
111{
112 return new SeriesRequestGenerator(this);
113}
| 70 PacketPtr pkt = new Packet(req, cmd);
71 uint8_t* dummyData = new uint8_t;
72 *dummyData = 0;
73 pkt->dataDynamic(dummyData);
74
75 if (port->sendTimingReq(pkt)) {
76 DPRINTF(DirectedTest, "initiating request - successful\n");
77 m_status = SeriesRequestGeneratorStatus_Request_Pending;
78 return true;
79 } else {
80 // If the packet did not issue, must delete
81 // Note: No need to delete the data, the packet destructor
82 // will delete it
83 delete pkt->req;
84 delete pkt;
85
86 DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
87 return false;
88 }
89}
90
91void
92SeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
93{
94 assert(m_active_node == proc);
95 assert(m_address == address);
96 assert(m_status == SeriesRequestGeneratorStatus_Request_Pending);
97
98 m_status = SeriesRequestGeneratorStatus_Thinking;
99 m_active_node++;
100 if (m_active_node == m_num_cpus) {
101 //
102 // Cycle of requests completed, increment cycle completions and restart
103 // at cpu zero
104 //
105 m_directed_tester->incrementCycleCompletions();
106 m_address += m_addr_increment_size;
107 m_active_node = 0;
108 }
109}
110
111SeriesRequestGenerator *
112SeriesRequestGeneratorParams::create()
113{
114 return new SeriesRequestGenerator(this);
115}
|