1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
31
32#include "base/random.hh"
| 1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
31
32#include "base/random.hh"
|
33#include "cpu/testers/directedtest/DirectedGenerator.hh"
34#include "cpu/testers/directedtest/RubyDirectedTester.hh"
35#include "debug/DirectedTest.hh"
36
37SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
38 : DirectedGenerator(p),
39 m_addr_increment_size(p->addr_increment_size),
40 m_percent_writes(p->percent_writes)
41{
42 m_status = SeriesRequestGeneratorStatus_Thinking;
43 m_active_node = 0;
44 m_address = 0x0;
45}
46
47SeriesRequestGenerator::~SeriesRequestGenerator()
48{
49}
50
51bool
52SeriesRequestGenerator::initiate()
53{
54 DPRINTF(DirectedTest, "initiating request\n");
55 assert(m_status == SeriesRequestGeneratorStatus_Thinking);
56
57 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
58
59 Request::Flags flags;
60
61 // For simplicity, requests are assumed to be 1 byte-sized
62 Request *req = new Request(m_address, 1, flags, masterId);
63
64 Packet::Command cmd;
65 bool do_write = (random_mt.random(0, 100) < m_percent_writes);
66 if (do_write) {
67 cmd = MemCmd::WriteReq;
68 } else {
69 cmd = MemCmd::ReadReq;
70 }
71
72 PacketPtr pkt = new Packet(req, cmd);
73 pkt->allocate();
74
75 if (port->sendTimingReq(pkt)) {
76 DPRINTF(DirectedTest, "initiating request - successful\n");
77 m_status = SeriesRequestGeneratorStatus_Request_Pending;
78 return true;
79 } else {
80 // If the packet did not issue, must delete
81 // Note: No need to delete the data, the packet destructor
82 // will delete it
83 delete pkt->req;
84 delete pkt;
85
86 DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
87 return false;
88 }
89}
90
91void
92SeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
93{
94 assert(m_active_node == proc);
95 assert(m_address == address);
96 assert(m_status == SeriesRequestGeneratorStatus_Request_Pending);
97
98 m_status = SeriesRequestGeneratorStatus_Thinking;
99 m_active_node++;
100 if (m_active_node == m_num_cpus) {
101 //
102 // Cycle of requests completed, increment cycle completions and restart
103 // at cpu zero
104 //
105 m_directed_tester->incrementCycleCompletions();
106 m_address += m_addr_increment_size;
107 m_active_node = 0;
108 }
109}
110
111SeriesRequestGenerator *
112SeriesRequestGeneratorParams::create()
113{
114 return new SeriesRequestGenerator(this);
115}
| 34#include "cpu/testers/directedtest/DirectedGenerator.hh"
35#include "cpu/testers/directedtest/RubyDirectedTester.hh"
36#include "debug/DirectedTest.hh"
37
38SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
39 : DirectedGenerator(p),
40 m_addr_increment_size(p->addr_increment_size),
41 m_percent_writes(p->percent_writes)
42{
43 m_status = SeriesRequestGeneratorStatus_Thinking;
44 m_active_node = 0;
45 m_address = 0x0;
46}
47
48SeriesRequestGenerator::~SeriesRequestGenerator()
49{
50}
51
52bool
53SeriesRequestGenerator::initiate()
54{
55 DPRINTF(DirectedTest, "initiating request\n");
56 assert(m_status == SeriesRequestGeneratorStatus_Thinking);
57
58 MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
59
60 Request::Flags flags;
61
62 // For simplicity, requests are assumed to be 1 byte-sized
63 Request *req = new Request(m_address, 1, flags, masterId);
64
65 Packet::Command cmd;
66 bool do_write = (random_mt.random(0, 100) < m_percent_writes);
67 if (do_write) {
68 cmd = MemCmd::WriteReq;
69 } else {
70 cmd = MemCmd::ReadReq;
71 }
72
73 PacketPtr pkt = new Packet(req, cmd);
74 pkt->allocate();
75
76 if (port->sendTimingReq(pkt)) {
77 DPRINTF(DirectedTest, "initiating request - successful\n");
78 m_status = SeriesRequestGeneratorStatus_Request_Pending;
79 return true;
80 } else {
81 // If the packet did not issue, must delete
82 // Note: No need to delete the data, the packet destructor
83 // will delete it
84 delete pkt->req;
85 delete pkt;
86
87 DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
88 return false;
89 }
90}
91
92void
93SeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
94{
95 assert(m_active_node == proc);
96 assert(m_address == address);
97 assert(m_status == SeriesRequestGeneratorStatus_Request_Pending);
98
99 m_status = SeriesRequestGeneratorStatus_Thinking;
100 m_active_node++;
101 if (m_active_node == m_num_cpus) {
102 //
103 // Cycle of requests completed, increment cycle completions and restart
104 // at cpu zero
105 //
106 m_directed_tester->incrementCycleCompletions();
107 m_address += m_addr_increment_size;
108 m_active_node = 0;
109 }
110}
111
112SeriesRequestGenerator *
113SeriesRequestGeneratorParams::create()
114{
115 return new SeriesRequestGenerator(this);
116}
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