RubyDirectedTester.py (13665:9c7fe3811b88) RubyDirectedTester.py (13892:0182a0601f66)
1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Brad Beckmann
28
29from m5.SimObject import SimObject
30from m5.params import *
31from m5.proxy import *
32
1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 16 unchanged lines hidden (view full) ---

25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Brad Beckmann
28
29from m5.SimObject import SimObject
30from m5.params import *
31from m5.proxy import *
32
33from m5.objects.MemObject import MemObject
33from m5.objects.ClockedObject import ClockedObject
34
35class DirectedGenerator(SimObject):
36 type = 'DirectedGenerator'
37 abstract = True
38 cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
39 num_cpus = Param.Int("num of cpus")
40 system = Param.System(Parent.any, "System we belong to")
41

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47 "number of different address streams to generate")
48 percent_writes = Param.Percent(50, "percent of access that are writes")
49
50class InvalidateGenerator(DirectedGenerator):
51 type = 'InvalidateGenerator'
52 cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
53 addr_increment_size = Param.Int(64, "address increment size")
54
34
35class DirectedGenerator(SimObject):
36 type = 'DirectedGenerator'
37 abstract = True
38 cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
39 num_cpus = Param.Int("num of cpus")
40 system = Param.System(Parent.any, "System we belong to")
41

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47 "number of different address streams to generate")
48 percent_writes = Param.Percent(50, "percent of access that are writes")
49
50class InvalidateGenerator(DirectedGenerator):
51 type = 'InvalidateGenerator'
52 cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
53 addr_increment_size = Param.Int(64, "address increment size")
54
55class RubyDirectedTester(MemObject):
55class RubyDirectedTester(ClockedObject):
56 type = 'RubyDirectedTester'
57 cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
58 cpuPort = VectorMasterPort("the cpu ports")
59 requests_to_complete = Param.Int("checks to complete")
60 generator = Param.DirectedGenerator("the request generator")
56 type = 'RubyDirectedTester'
57 cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
58 cpuPort = VectorMasterPort("the cpu ports")
59 requests_to_complete = Param.Int("checks to complete")
60 generator = Param.DirectedGenerator("the request generator")