1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 20 unchanged lines hidden (view full) --- 29from m5.SimObject import SimObject 30from MemObject import MemObject 31from m5.params import * 32from m5.proxy import * 33 34class DirectedGenerator(SimObject): 35 type = 'DirectedGenerator' 36 abstract = True |
37 cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh" |
38 num_cpus = Param.Int("num of cpus") 39 system = Param.System(Parent.any, "System we belong to") 40 41class SeriesRequestGenerator(DirectedGenerator): 42 type = 'SeriesRequestGenerator' |
43 cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh" |
44 addr_increment_size = Param.Int(64, "address increment size") 45 issue_writes = Param.Bool(True, "issue writes if true, otherwise reads") 46 47class InvalidateGenerator(DirectedGenerator): 48 type = 'InvalidateGenerator' |
49 cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh" |
50 addr_increment_size = Param.Int(64, "address increment size") 51 52class RubyDirectedTester(MemObject): 53 type = 'RubyDirectedTester' |
54 cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh" |
55 cpuPort = VectorMasterPort("the cpu ports") 56 requests_to_complete = Param.Int("checks to complete") 57 generator = Param.DirectedGenerator("the request generator") |