1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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30from MemObject import MemObject
31from m5.params import *
32from m5.proxy import *
33
34class DirectedGenerator(SimObject):
35 type = 'DirectedGenerator'
36 abstract = True
37 num_cpus = Param.Int("num of cpus")
38 system = Param.System(Parent.any, "System we belong to")
39
40class SeriesRequestGenerator(DirectedGenerator):
41 type = 'SeriesRequestGenerator'
42 addr_increment_size = Param.Int(64, "address increment size")
43 issue_writes = Param.Bool(True, "issue writes if true, otherwise reads")
44
45class InvalidateGenerator(DirectedGenerator):
46 type = 'InvalidateGenerator'
47 addr_increment_size = Param.Int(64, "address increment size")
48
49class RubyDirectedTester(MemObject):
50 type = 'RubyDirectedTester'
51 cpuPort = VectorPort("the cpu ports")
52 requests_to_complete = Param.Int("checks to complete")
53 generator = Param.DirectedGenerator("the request generator")