static_inst.hh (9920:028e4da64b42) static_inst.hh (10201:30a20d2072c1)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
47#include "sim/fault_fwd.hh"
48
49// forward declarations
50class Packet;
51
52struct O3CPUImpl;
53template <class Impl> class BaseO3DynInst;
54typedef BaseO3DynInst<O3CPUImpl> O3DynInst;

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67/**
68 * Base, ISA-independent static instruction class.
69 *
70 * The main component of this class is the vector of flags and the
71 * associated methods for reading them. Any object that can rely
72 * solely on these flags can process instructions without being
73 * recompiled for multiple ISAs.
74 */
48#include "sim/fault_fwd.hh"
49
50// forward declarations
51class Packet;
52
53struct O3CPUImpl;
54template <class Impl> class BaseO3DynInst;
55typedef BaseO3DynInst<O3CPUImpl> O3DynInst;

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68/**
69 * Base, ISA-independent static instruction class.
70 *
71 * The main component of this class is the vector of flags and the
72 * associated methods for reading them. Any object that can rely
73 * solely on these flags can process instructions without being
74 * recompiled for multiple ISAs.
75 */
75class StaticInst : public RefCounted
76class StaticInst : public RefCounted, public StaticInstFlags
76{
77 public:
78 /// Binary extended machine instruction type.
79 typedef TheISA::ExtMachInst ExtMachInst;
80 /// Logical register index type.
81 typedef TheISA::RegIndex RegIndex;
82
83 enum {
84 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
85 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
86 };
87
77{
78 public:
79 /// Binary extended machine instruction type.
80 typedef TheISA::ExtMachInst ExtMachInst;
81 /// Logical register index type.
82 typedef TheISA::RegIndex RegIndex;
83
84 enum {
85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
86 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
87 };
88
88 /// Set of boolean static instruction properties.
89 ///
90 /// Notes:
91 /// - The IsInteger and IsFloating flags are based on the class of
92 /// registers accessed by the instruction. Although most
93 /// instructions will have exactly one of these two flags set, it
94 /// is possible for an instruction to have neither (e.g., direct
95 /// unconditional branches, memory barriers) or both (e.g., an
96 /// FP/int conversion).
97 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
98 /// will be set.
99 /// - If IsControl is set, then exactly one of IsDirectControl or
100 /// IsIndirect Control will be set, and exactly one of
101 /// IsCondControl or IsUncondControl will be set.
102 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
103 /// implemented as flags since in the current model there's no
104 /// other way for instructions to inject behavior into the
105 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
106 /// model we should be able to get rid of these flags and
107 /// implement this behavior via the execute() methods.
108 ///
109 enum Flags {
110 IsNop, ///< Is a no-op (no effect at all).
111
112 IsInteger, ///< References integer regs.
113 IsFloating, ///< References FP regs.
114 IsCC, ///< References CC regs.
115
116 IsMemRef, ///< References memory (load, store, or prefetch).
117 IsLoad, ///< Reads from memory (load or prefetch).
118 IsStore, ///< Writes to memory.
119 IsStoreConditional, ///< Store conditional instruction.
120 IsIndexed, ///< Accesses memory with an indexed address computation
121 IsInstPrefetch, ///< Instruction-cache prefetch.
122 IsDataPrefetch, ///< Data-cache prefetch.
123
124 IsControl, ///< Control transfer instruction.
125 IsDirectControl, ///< PC relative control transfer.
126 IsIndirectControl, ///< Register indirect control transfer.
127 IsCondControl, ///< Conditional control transfer.
128 IsUncondControl, ///< Unconditional control transfer.
129 IsCall, ///< Subroutine call.
130 IsReturn, ///< Subroutine return.
131
132 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
133
134 IsThreadSync, ///< Thread synchronization operation.
135
136 IsSerializing, ///< Serializes pipeline: won't execute until all
137 /// older instructions have committed.
138 IsSerializeBefore,
139 IsSerializeAfter,
140 IsMemBarrier, ///< Is a memory barrier
141 IsWriteBarrier, ///< Is a write barrier
142 IsReadBarrier, ///< Is a read barrier
143 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
144
145 IsNonSpeculative, ///< Should not be executed speculatively
146 IsQuiesce, ///< Is a quiesce instruction
147
148 IsIprAccess, ///< Accesses IPRs
149 IsUnverifiable, ///< Can't be verified by a checker
150
151 IsSyscall, ///< Causes a system call to be emulated in syscall
152 /// emulation mode.
153
154 //Flags for microcode
155 IsMacroop, ///< Is a macroop containing microops
156 IsMicroop, ///< Is a microop
157 IsDelayedCommit, ///< This microop doesn't commit right away
158 IsLastMicroop, ///< This microop ends a microop sequence
159 IsFirstMicroop, ///< This microop begins a microop sequence
160 //This flag doesn't do anything yet
161 IsMicroBranch, ///< This microop branches within the microcode for a macroop
162 IsDspOp,
163 IsSquashAfter, ///< Squash all uncommitted state after executed
164 NumFlags
165 };
166
167 protected:
168
169 /// Flag values for this instruction.
89 protected:
90
91 /// Flag values for this instruction.
170 std::bitset flags;
92 std::bitset<Num_Flags> flags;
171
172 /// See opClass().
173 OpClass _opClass;
174
175 /// See numSrcRegs().
176 int8_t _numSrcRegs;
177
178 /// See numDestRegs().

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382 * The default version of this function will call the internal
383 * virtual generateDisassembly() function to get the string,
384 * then cache it in #cachedDisassembly. If the disassembly
385 * should not be cached, this function should be overridden directly.
386 */
387 virtual const std::string &disassemble(Addr pc,
388 const SymbolTable *symtab = 0) const;
389
93
94 /// See opClass().
95 OpClass _opClass;
96
97 /// See numSrcRegs().
98 int8_t _numSrcRegs;
99
100 /// See numDestRegs().

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304 * The default version of this function will call the internal
305 * virtual generateDisassembly() function to get the string,
306 * then cache it in #cachedDisassembly. If the disassembly
307 * should not be cached, this function should be overridden directly.
308 */
309 virtual const std::string &disassemble(Addr pc,
310 const SymbolTable *symtab = 0) const;
311
312 /**
313 * Print a separator separated list of this instruction's set flag
314 * names on the given stream.
315 */
316 void printFlags(std::ostream &outs, const std::string &separator) const;
317
390 /// Return name of machine instruction
391 std::string getName() { return mnemonic; }
392};
393
394#endif // __CPU_STATIC_INST_HH__
318 /// Return name of machine instruction
319 std::string getName() { return mnemonic; }
320};
321
322#endif // __CPU_STATIC_INST_HH__